[llvm] b9257a3 - RISCVMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 16:14:04 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T16:13:58-07:00
New Revision: b9257a34a9e02bdc0ea19d9ac67294f788ab0b9b
URL: https://github.com/llvm/llvm-project/commit/b9257a34a9e02bdc0ea19d9ac67294f788ab0b9b
DIFF: https://github.com/llvm/llvm-project/commit/b9257a34a9e02bdc0ea19d9ac67294f788ab0b9b.diff
LOG: RISCVMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index d298ce769c1dc..7f7bbfa91fc5b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -69,25 +69,23 @@ MCFixupKindInfo RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_riscv_lo12_i", 20, 12, 0},
{"fixup_riscv_12_i", 20, 12, 0},
{"fixup_riscv_lo12_s", 0, 32, 0},
- {"fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_pcrel_lo12_i", 20, 12,
- MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
- {"fixup_riscv_pcrel_lo12_s", 0, 32,
- MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
- {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
-
- {"fixup_riscv_qc_e_branch", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_riscv_pcrel_hi20", 12, 20, 0},
+ {"fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsTarget},
+ {"fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsTarget},
+ {"fixup_riscv_jal", 12, 20, 0},
+ {"fixup_riscv_branch", 0, 32, 0},
+ {"fixup_riscv_rvc_jump", 2, 11, 0},
+ {"fixup_riscv_rvc_branch", 0, 16, 0},
+ {"fixup_riscv_call", 0, 64, 0},
+ {"fixup_riscv_call_plt", 0, 64, 0},
+
+ {"fixup_riscv_qc_e_branch", 0, 48, 0},
{"fixup_riscv_qc_e_32", 16, 32, 0},
{"fixup_riscv_qc_abs20_u", 12, 20, 0},
- {"fixup_riscv_qc_e_call_plt", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_riscv_qc_e_call_plt", 0, 48, 0},
// Andes fixups
- {"fixup_riscv_nds_branch_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_riscv_nds_branch_10", 0, 32, 0},
};
static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
"Not all fixup kinds added to Infos array");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index e13b201369c71..2ed7cd9f008a6 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -120,6 +120,28 @@ MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
return new RISCVMCCodeEmitter(Ctx, MCII);
}
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case ELF::R_RISCV_CALL_PLT:
+ case RISCV::fixup_riscv_pcrel_hi20:
+ case RISCV::fixup_riscv_pcrel_lo12_i:
+ case RISCV::fixup_riscv_pcrel_lo12_s:
+ case RISCV::fixup_riscv_jal:
+ case RISCV::fixup_riscv_branch:
+ case RISCV::fixup_riscv_rvc_jump:
+ case RISCV::fixup_riscv_rvc_branch:
+ case RISCV::fixup_riscv_call:
+ case RISCV::fixup_riscv_call_plt:
+ case RISCV::fixup_riscv_qc_e_branch:
+ case RISCV::fixup_riscv_qc_e_call_plt:
+ case RISCV::fixup_riscv_nds_branch_10:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
// relocation types. We expand those pseudo-instructions while encoding them,
// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
@@ -181,7 +203,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
MCRegister Link = MI.getOperand(0).getReg();
MCRegister Dest = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
- Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TLSDESC_CALL));
+ addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);
MCInst Call =
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
@@ -208,7 +230,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
"Expected tprel_add relocation on TP-relative symbol");
- Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TPREL_ADD));
+ addFixup(Fixups, 0, Expr, ELF::R_RISCV_TPREL_ADD);
if (STI.hasFeature(RISCV::FeatureRelax))
Fixups.back().setLinkerRelaxable();
@@ -318,10 +340,8 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
// Drop any fixup added so we can add the correct one.
Fixups.resize(FixupStartIndex);
- if (SrcSymbol.isExpr()) {
- Fixups.push_back(
- MCFixup::create(Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal));
- }
+ if (SrcSymbol.isExpr())
+ addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
}
// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
@@ -368,10 +388,8 @@ void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
support::endian::write(CB, JBinary, llvm::endianness::little);
// Drop any fixup added so we can add the correct one.
Fixups.resize(FixupStartIndex);
- if (SrcSymbol.isExpr()) {
- Fixups.push_back(
- MCFixup::create(Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal));
- }
+ if (SrcSymbol.isExpr())
+ addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
}
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
@@ -649,7 +667,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
- Fixups.push_back(MCFixup::create(0, Expr, FixupKind));
+ addFixup(Fixups, 0, Expr, FixupKind);
// If linker relaxation is enabled and supported by this relocation, set
// a bit so that if fixup is unresolved, a R_RISCV_RELAX relocation will be
// appended.
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