[llvm] 20b3ab5 - MCFixup: Remove unused Loc argument
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 12:23:10 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T12:23:04-07:00
New Revision: 20b3ab5683c62ac455f010cbce1a625cfd90bedd
URL: https://github.com/llvm/llvm-project/commit/20b3ab5683c62ac455f010cbce1a625cfd90bedd
DIFF: https://github.com/llvm/llvm-project/commit/20b3ab5683c62ac455f010cbce1a625cfd90bedd.diff
LOG: MCFixup: Remove unused Loc argument
MCFixup::Loc has been removed in favor of MCExpr::Loc through
`const MCExpr *Value` (commit 777391a2164b89d2030ca013562151ca3c3676d1).
Added:
Modified:
llvm/include/llvm/MC/MCFixup.h
llvm/lib/MC/MCObjectStreamer.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCFixup.h b/llvm/include/llvm/MC/MCFixup.h
index 091d72eb129ea..bf33d66cc1113 100644
--- a/llvm/include/llvm/MC/MCFixup.h
+++ b/llvm/include/llvm/MC/MCFixup.h
@@ -90,9 +90,8 @@ class MCFixup {
FI.Kind = Kind;
return FI;
}
- static MCFixup create(uint32_t Offset, const MCExpr *Value, unsigned Kind,
- SMLoc Loc = SMLoc()) {
- return create(Offset, Value, MCFixupKind(Kind), Loc);
+ static MCFixup create(uint32_t Offset, const MCExpr *Value, unsigned Kind) {
+ return create(Offset, Value, MCFixupKind(Kind));
}
MCFixupKind getKind() const { return Kind; }
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index 62b261a1268bc..bd1a77467679b 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -188,7 +188,7 @@ void MCObjectStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
return;
}
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
- MCFixup::getDataKindForSize(Size), Loc));
+ MCFixup::getDataKindForSize(Size)));
DF->appendContents(Size, 0);
}
@@ -696,7 +696,7 @@ MCObjectStreamer::emitRelocDirective(const MCExpr &Offset, StringRef Name,
if (OffsetVal.isAbsolute()) {
if (OffsetVal.getConstant() < 0)
return std::make_pair(false, std::string(".reloc offset is negative"));
- DF->addFixup(MCFixup::create(OffsetVal.getConstant(), Expr, Kind, Loc));
+ DF->addFixup(MCFixup::create(OffsetVal.getConstant(), Expr, Kind));
return std::nullopt;
}
if (OffsetVal.getSubSym())
@@ -712,13 +712,13 @@ MCObjectStreamer::emitRelocDirective(const MCExpr &Offset, StringRef Name,
if (Error != std::nullopt)
return Error;
- DF->addFixup(MCFixup::create(SymbolOffset + OffsetVal.getConstant(), Expr,
- Kind, Loc));
+ DF->addFixup(
+ MCFixup::create(SymbolOffset + OffsetVal.getConstant(), Expr, Kind));
return std::nullopt;
}
PendingFixups.emplace_back(
- &Symbol, DF, MCFixup::create(OffsetVal.getConstant(), Expr, Kind, Loc));
+ &Symbol, DF, MCFixup::create(OffsetVal.getConstant(), Expr, Kind));
return std::nullopt;
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index a1034934e646d..7e93e5be30641 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -248,7 +248,7 @@ AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
else {
assert(MO.isExpr() && "unable to encode load/store imm operand");
MCFixupKind Kind = MCFixupKind(FixupKind);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
}
@@ -272,7 +272,7 @@ AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
MCNumFixups += 1;
@@ -302,7 +302,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
// Encode the 12 bits of the fixup.
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
++MCNumFixups;
@@ -330,7 +330,7 @@ uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
@@ -351,7 +351,7 @@ uint32_t AArch64MCCodeEmitter::getCondCompBranchTargetOpValue(
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch9);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
@@ -374,7 +374,7 @@ AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch16);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
@@ -396,7 +396,7 @@ AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
@@ -423,8 +423,8 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
return MO.getImm();
assert(MO.isExpr() && "Unexpected movz/movk immediate");
- Fixups.push_back(MCFixup::create(
- 0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(),
+ MCFixupKind(AArch64::fixup_aarch64_movw)));
++MCNumFixups;
@@ -444,7 +444,7 @@ uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
assert(MO.isExpr() && "Unexpected ADR target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
@@ -468,7 +468,7 @@ AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
MCFixupKind Kind = MI.getOpcode() == AArch64::BL
? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumFixups;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index abb5003f3320b..9cda61fb744cd 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -446,7 +446,7 @@ void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
Op = APInt::getZero(96);
} else {
getMachineOpValue(MI, MO, Op, Fixups, STI);
@@ -662,7 +662,7 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
uint32_t Offset = Desc.getSize();
assert(Offset == 4 || Offset == 8);
- Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind));
}
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 8195c93d847b0..02a2b06d0951c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -166,7 +166,7 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
// We can't easily get the order of the current one, so compare against
// the first one and adjust offset.
const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
- Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4));
return 0;
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index fba32eae4dfa8..5c1c569ddcd3d 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -321,7 +321,7 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
const MCExpr *Expr = MO.getExpr();
// Fixups resolve to plain values that need to be encoded.
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
return 0;
}
@@ -340,7 +340,7 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
const MCExpr *Expr = MO.getExpr();
// Fixups resolve to plain values that need to be encoded.
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
return 0;
}
unsigned SoImm = MO.getImm();
@@ -616,7 +616,7 @@ static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FixupKind);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
@@ -979,7 +979,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
isAdd = false; // 'U' bit is set as part of the fixup.
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
- Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind));
}
} else if (MO.isExpr()) {
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
@@ -989,7 +989,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
else
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
++MCNumCPRelocations;
} else {
@@ -1114,7 +1114,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
++MCNumCPRelocations;
} else
@@ -1251,7 +1251,7 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
break;
}
- Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, E, Kind));
return 0;
}
// If the expression doesn't have :upper16:, :lower16: on it, it's just a
@@ -1373,7 +1373,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
++MCNumCPRelocations;
return (Rn << 9) | (1 << 13);
@@ -1455,7 +1455,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
++MCNumCPRelocations;
} else {
@@ -1495,7 +1495,7 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
- Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind));
++MCNumCPRelocations;
} else {
@@ -1950,7 +1950,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
MO.getExpr(), BranchMO.getExpr(), CTX);
MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
- Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
+ Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind));
return 0;
}
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
index 4934e1c71bc03..d1a09fb5b2bec 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
@@ -110,8 +110,7 @@ AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
- Fixups.push_back(
- MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup)));
return 0;
}
@@ -156,8 +155,8 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
OffsetBits = OffsetOp.getImm();
} else if (OffsetOp.isExpr()) {
OffsetBits = 0;
- Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
- MCFixupKind(AVR::fixup_6), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6)));
} else {
llvm_unreachable("Invalid value for offset");
}
@@ -191,8 +190,7 @@ unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
}
MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
- Fixups.push_back(
- MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), FixupKind));
return 0;
}
@@ -208,7 +206,7 @@ unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
if (MO.isExpr()) {
MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind));
return 0;
}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
index 32cccdd5405ba..3b9176d218099 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
@@ -57,7 +57,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
assert(MO.isExpr() && "Unexpected MO type.");
MCFixupKind Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
@@ -110,7 +110,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
@@ -125,7 +125,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
@@ -140,7 +140,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
@@ -154,7 +154,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
@@ -168,7 +168,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
if (MO.getExpr()->getKind() == MCExpr::Specifier)
Kind = getTargetFixup(MO.getExpr());
- Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
return 0;
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 75917e27eb0fd..8490e74b4d959 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -698,8 +698,8 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
}
- MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
- MCFixupKind(FixupKind), MI.getLoc());
+ MCFixup Fixup =
+ MCFixup::create(State.Addend, FixupExpr, MCFixupKind(FixupKind));
Fixups.push_back(Fixup);
// All of the information is in the fixup.
return 0;
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
index 5ad550e380380..970efb01c40d5 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
@@ -195,8 +195,7 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
"Unhandled expression!");
- Fixups.push_back(
- MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
// If linker relaxation is enabled and supported by this relocation, set
// a bit so that if fixup is unresolved, a R_LARCH_RELAX relocation will be
// appended.
@@ -249,8 +248,7 @@ void LoongArchMCCodeEmitter::expandAddTPRel(const MCInst &MI,
"Expected %le_add_r relocation on TP-relative symbol");
// Emit the correct %le_add_r relocation for the symbol.
- Fixups.push_back(
- MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R));
if (STI.hasFeature(LoongArch::FeatureRelax))
Fixups.back().setLinkerRelaxable();
diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
index 35a7da4fbe5a2..5d05ef0863f8f 100644
--- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
+++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
@@ -111,8 +111,8 @@ unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI,
}
assert(MO.isExpr() && "Expected expr operand");
- Fixups.push_back(MCFixup::create(Offset, MO.getExpr(),
- static_cast<MCFixupKind>(MSP430::fixup_16_byte), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(
+ Offset, MO.getExpr(), static_cast<MCFixupKind>(MSP430::fixup_16_byte)));
Offset += 2;
return 0;
}
@@ -144,7 +144,7 @@ unsigned MSP430MCCodeEmitter::getMemOpValue(const MCInst &MI, unsigned Op,
break;
}
Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(),
- static_cast<MCFixupKind>(FixupKind), MI.getLoc()));
+ static_cast<MCFixupKind>(FixupKind)));
Offset += 2;
return Reg;
}
@@ -157,8 +157,8 @@ unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(const MCInst &MI, unsigned Op,
return MO.getImm();
assert(MO.isExpr() && "Expr operand expected");
- Fixups.push_back(MCFixup::create(0, MO.getExpr(),
- static_cast<MCFixupKind>(MSP430::fixup_10_pcrel), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(
+ 0, MO.getExpr(), static_cast<MCFixupKind>(MSP430::fixup_10_pcrel)));
return 0;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 0fa0c36f5aaaa..592af18a969a1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -885,7 +885,7 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
MCContext &Ctx = getContext();
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
- MCFixup Fixup = MCFixup::create(0, Dummy, ELF::R_RISCV_ALIGN, SMLoc());
+ MCFixup Fixup = MCFixup::create(0, Dummy, ELF::R_RISCV_ALIGN);
uint64_t FixedValue = 0;
MCValue NopBytes = MCValue::get(Count);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index ce0fbc0ac0654..421da06aa4993 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -181,8 +181,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
MCRegister Link = MI.getOperand(0).getReg();
MCRegister Dest = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
- Fixups.push_back(
- MCFixup::create(0, Expr, ELF::R_RISCV_TLSDESC_CALL, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TLSDESC_CALL));
MCInst Call =
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
@@ -209,8 +208,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
"Expected tprel_add relocation on TP-relative symbol");
- Fixups.push_back(
- MCFixup::create(0, Expr, ELF::R_RISCV_TPREL_ADD, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TPREL_ADD));
if (STI.hasFeature(RISCV::FeatureRelax))
Fixups.back().setLinkerRelaxable();
@@ -653,7 +651,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
- Fixups.push_back(MCFixup::create(0, Expr, FixupKind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, FixupKind));
// If linker relaxation is enabled and supported by this relocation, set
// a bit so that if fixup is unresolved, a R_RISCV_RELAX relocation will be
// appended.
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
index 3e5e2aca769cb..e7c61e2b2f434 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
@@ -170,8 +170,8 @@ uint64_t SystemZMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNum,
unsigned OpBitSize =
SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind].TargetSize;
uint32_t BitOffset = MIBitSize - RawBitOffset - OpBitSize;
- Fixups.push_back(MCFixup::create(BitOffset >> 3, MO.getExpr(),
- (MCFixupKind)Kind, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(BitOffset >> 3, MO.getExpr(), (MCFixupKind)Kind));
return 0;
}
llvm_unreachable("Unexpected operand type!");
@@ -206,13 +206,13 @@ SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx, Loc);
}
}
- Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind, Loc));
+ Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind));
// Output the fixup for the TLS marker if present.
if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
- Fixups.push_back(MCFixup::create(
- 0, MOTLS.getExpr(), (MCFixupKind)SystemZ::FK_390_TLS_CALL, Loc));
+ Fixups.push_back(MCFixup::create(0, MOTLS.getExpr(),
+ (MCFixupKind)SystemZ::FK_390_TLS_CALL));
}
return 0;
}
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
index 807fd42b8cf6e..1097bf7cbb4f8 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
@@ -183,8 +183,8 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
assert(Opcode == WebAssembly::TRY_TABLE_S);
FixupKind = MCFixupKind(WebAssembly::fixup_uleb128_i32);
}
- Fixups.push_back(MCFixup::create(OS.tell() - Start, MO.getExpr(),
- FixupKind, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(OS.tell() - Start, MO.getExpr(), FixupKind));
++MCNumFixups;
encodeULEB128(0, OS, PaddedSize);
} else {
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 11bd3b0efde3e..fbffc93a6392f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -607,7 +607,7 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
// Emit a symbolic constant as a fixup and 4 zeros.
Fixups.push_back(MCFixup::create(static_cast<uint32_t>(CB.size() - StartByte),
- Expr, FixupKind, Loc));
+ Expr, FixupKind));
emitConstant(0, Size, CB);
}
@@ -812,7 +812,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
if (Sym && Sym->getSpecifier() == X86::S_TLSCALL) {
// This is exclusively used by call *a at tlscall(base). The relocation
// (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
- Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Sym, FK_NONE));
emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
return;
}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
index 02bac7a05982b..5228f84f05d4a 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -195,8 +195,8 @@ XtensaMCCodeEmitter::getJumpTargetEncoding(const MCInst &MI, unsigned int OpNum,
return MO.getImm();
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_jump_18), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_jump_18)));
return 0;
}
@@ -213,17 +213,17 @@ uint32_t XtensaMCCodeEmitter::getBranchTargetEncoding(
case Xtensa::BGEZ:
case Xtensa::BLTZ:
case Xtensa::BNEZ:
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_12), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_12)));
return 0;
case Xtensa::BEQZ_N:
case Xtensa::BNEZ_N:
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_6), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_6)));
return 0;
default:
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_8), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_branch_8)));
return 0;
}
}
@@ -240,8 +240,8 @@ XtensaMCCodeEmitter::getLoopTargetEncoding(const MCInst &MI, unsigned int OpNum,
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_loop_8), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_loop_8)));
return 0;
}
@@ -261,8 +261,8 @@ XtensaMCCodeEmitter::getCallEncoding(const MCInst &MI, unsigned int OpNum,
assert((MO.isExpr()) && "Unexpected operand value!");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(Xtensa::fixup_xtensa_call_18), MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, MCFixupKind(Xtensa::fixup_xtensa_call_18)));
return 0;
}
@@ -281,8 +281,8 @@ XtensaMCCodeEmitter::getL32RTargetEncoding(const MCInst &MI, unsigned OpNum,
assert((MO.isExpr()) && "Unexpected operand value!");
- Fixups.push_back(MCFixup::create(
- 0, MO.getExpr(), MCFixupKind(Xtensa::fixup_xtensa_l32r_16), MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(),
+ MCFixupKind(Xtensa::fixup_xtensa_l32r_16)));
return 0;
}
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