[llvm] [DAG] visitXOR - convert ISD::ABS matching to SDPatternMatch. NFC. (PR #147079)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/147079

Lets us remove all the horrible commutative handling

>From 98c6583bb34dd565934a48da328b3d8d3e75b497 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 4 Jul 2025 16:28:39 +0100
Subject: [PATCH] [DAG] visitXOR - convert ISD::ABS matching to SDPatternMatch

Lets us remove all the horrible commutative handling
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 55f994f357b75..3daa65d3cb324 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10001,15 +10001,11 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
 
   // fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X)
   if (!LegalOperations || hasOperation(ISD::ABS, VT)) {
-    SDValue A = N0Opcode == ISD::ADD ? N0 : N1;
-    SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
-    if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
-      SDValue A0 = A.getOperand(0), A1 = A.getOperand(1);
-      SDValue S0 = S.getOperand(0);
-      if ((A0 == S && A1 == S0) || (A1 == S && A0 == S0))
-        if (ConstantSDNode *C = isConstOrConstSplat(S.getOperand(1)))
-          if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1))
-            return DAG.getNode(ISD::ABS, DL, VT, S0);
+    SDValue X, Y;
+    if (sd_match(N, m_Xor(m_Add(m_Value(X), m_Value(Y)), m_Deferred(Y))) &&
+        sd_match(Y, m_Sra(m_Specific(X),
+                          m_SpecificInt(VT.getScalarSizeInBits() - 1)))) {
+      return DAG.getNode(ISD::ABS, DL, VT, X);
     }
   }