[llvm] [RISCV] AddEdge between first mask producer and user of V0 (PR #146855)

[Pengcheng Wang via llvm-commits]

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@@ -68,11 +68,33 @@ class RISCVVectorMaskDAGMutation : public ScheduleDAGMutation {
 
   void apply(ScheduleDAGInstrs *DAG) override {
     SUnit *NearestUseV0SU = nullptr;
+    SmallVector<SUnit *, 8> DefMask;
     for (SUnit &SU : DAG->SUnits) {
       const MachineInstr *MI = SU.getInstr();
-      if (MI->findRegisterUseOperand(RISCV::V0, TRI))
+      if (RISCVII::getLMul(MI->getDesc().TSFlags) != RISCVVType::LMUL_8 &&
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wangpc-pp wrote:

Do we really need this LMUL8 constraint here?

https://github.com/llvm/llvm-project/pull/146855