[llvm] 3c13257 - [RISCV] Rename XTHeadVdot instructions to match their mnemonic. NFC (#146953)

[via llvm-commits]

Author: Craig Topper
Date: 2025-07-03T13:43:34-07:00
New Revision: 3c13257f32f5669510860f5f40851e28270f36b3

URL: https://github.com/llvm/llvm-project/commit/3c13257f32f5669510860f5f40851e28270f36b3
DIFF: https://github.com/llvm/llvm-project/commit/3c13257f32f5669510860f5f40851e28270f36b3.diff

LOG: [RISCV] Rename XTHeadVdot instructions to match their mnemonic. NFC (#146953)

We were using the extension name as a prefix rather than TH_.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index c23a58ceccead..c0f7ab127aeb7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -476,10 +476,10 @@ def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,
 } // DecoderNamespace = "XTHead"
 
 let Predicates = [HasVendorXTHeadVdot] in {
-defm THVdotVMAQA      : THVdotVMAQA<"th.vmaqa",     0b100000>;
-defm THVdotVMAQAU     : THVdotVMAQA<"th.vmaqau",    0b100010>;
-defm THVdotVMAQASU    : THVdotVMAQA<"th.vmaqasu",   0b100100>;
-defm THVdotVMAQAUS    : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
+defm TH_VMAQA      : THVdotVMAQA<"th.vmaqa",     0b100000>;
+defm TH_VMAQAU     : THVdotVMAQA<"th.vmaqau",    0b100010>;
+defm TH_VMAQASU    : THVdotVMAQA<"th.vmaqasu",   0b100100>;
+defm TH_VMAQAUS    : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
 }
 
 // Associate LMUL with tablegen records of register classes.
@@ -661,20 +661,20 @@ def : Pat<(i32 (sub GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
 } // Predicates = [HasVendorXTHeadMac, IsRV32]
 
 let Predicates = [HasVendorXTHeadVdot] in {
-defm PseudoTHVdotVMAQA      : VPseudoVMAQA_VV_VX;
-defm PseudoTHVdotVMAQAU     : VPseudoVMAQA_VV_VX;
-defm PseudoTHVdotVMAQASU    : VPseudoVMAQA_VV_VX;
-defm PseudoTHVdotVMAQAUS    : VPseudoVMAQA_VX;
+defm PseudoTH_VMAQA      : VPseudoVMAQA_VV_VX;
+defm PseudoTH_VMAQAU     : VPseudoVMAQA_VV_VX;
+defm PseudoTH_VMAQASU    : VPseudoVMAQA_VV_VX;
+defm PseudoTH_VMAQAUS    : VPseudoVMAQA_VX;
 }
 
 let Predicates = [HasVendorXTHeadVdot] in {
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTHVdotVMAQA",
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTH_VMAQA",
                               AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU",
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTH_VMAQAU",
                               AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTH_VMAQASU",
                               AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus",   "PseudoTHVdotVMAQAUS",
+defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus",   "PseudoTH_VMAQAUS",
                            AllQuadWidenableInt8NoVLMulVectors>;
 }
 

diff  --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 15ae8d729a37e..2744dbc0907bf 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -376,7 +376,7 @@ TEST_P(RISCVInstrInfoTest, GetDestEEW) {
   EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VIOTA_M), 3), 3u);
   EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::SF_VQMACCU_2x8x2), 3), 5u);
   EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::SF_VFWMACC_4x4x4), 4), 5u);
-  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::THVdotVMAQA_VV), 5), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::TH_VMAQA_VV), 5), 5u);
 }
 
 } // namespace