[llvm] [RISCV] Fix crash when trying to remove segment (PR #146524)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 3 06:33:44 PDT 2025
https://github.com/sc-clulzze updated https://github.com/llvm/llvm-project/pull/146524
>From a809af511ea893b05833645d50edab944213d778 Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Tue, 1 Jul 2025 12:50:33 +0000
Subject: [PATCH 1/4] [RISCV] Fix crash when trying to remove segment
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 5 +-
llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll | 58 ++++++++++++++++++++
2 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 78d64ea67324f..bc4bf94d16042 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1768,8 +1768,9 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
SlotIndex NewDefSI =
LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
LiveInterval &DefLI = LIS->getInterval(VLOutput);
- VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex());
- DefLI.removeSegment(DefLI.beginIndex(), NewDefSI);
+ const auto *DefSeg = DefLI.getSegmentContaining(NewDefSI);
+ VNInfo *DefVNI = DefLI.getVNInfoAt(DefSeg->start);
+ DefLI.removeSegment(DefSeg->start, NewDefSI);
DefVNI->def = NewDefSI;
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
new file mode 100644
index 0000000000000..0da62d5a80046
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @strlen16_vec(ptr %s) {
+; CHECK-LABEL: strlen16_vec:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: li a3, -1
+; CHECK-NEXT: li a4, 16
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_1: # %while.body
+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: add a1, a6, a1
+; CHECK-NEXT: bne a5, a3, .LBB0_5
+; CHECK-NEXT: .LBB0_2: # %while.cond
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: bne a4, a2, .LBB0_5
+; CHECK-NEXT: # %bb.3: # %while.body
+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; CHECK-NEXT: vle16ff.v v8, (a0)
+; CHECK-NEXT: csrr a4, vl
+; CHECK-NEXT: vmseq.vi v8, v8, 0
+; CHECK-NEXT: vfirst.m a5, v8
+; CHECK-NEXT: mv a6, a4
+; CHECK-NEXT: beq a5, a3, .LBB0_1
+; CHECK-NEXT: # %bb.4: # %while.body
+; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: mv a6, a5
+; CHECK-NEXT: j .LBB0_1
+; CHECK-NEXT: .LBB0_5: # %while.end
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: ret
+entry:
+ br label %while.cond
+
+while.cond: ; preds = %while.body, %entry
+ %new_vl.0 = phi i64 [ 16, %entry ], [ %2, %while.body ]
+ %len.0 = phi i64 [ 0, %entry ], [ %len.1, %while.body ]
+ %cmp = icmp eq i64 %new_vl.0, 16
+ br i1 %cmp, label %while.body, label %while.end
+
+while.body: ; preds = %while.cond
+ %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> poison, ptr %s, i64 16)
+ %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 0
+ %2 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
+ %3 = tail call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> %1, i16 0, i64 %2)
+ %4 = tail call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %3, i64 %2)
+ %cmp1 = icmp eq i64 %4, -1
+ %.13 = select i1 %cmp1, i64 %2, i64 %4
+ %len.1 = add i64 %.13, %len.0
+ br i1 %cmp1, label %while.cond, label %while.end
+
+while.end: ; preds = %while.body, %while.cond
+ %len.2 = phi i64 [ %len.1, %while.body ], [ %len.0, %while.cond ]
+ ret i64 %len.2
+}
>From c1b6e129983c104c261738c6e8761276a59d9c34 Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Tue, 1 Jul 2025 15:44:41 +0000
Subject: [PATCH 2/4] Reduced and moved vleff-crash.ll to vsetvli-insert.ll
---
llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll | 58 -------------------
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 32 ++++++++++
2 files changed, 32 insertions(+), 58 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
deleted file mode 100644
index 0da62d5a80046..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vleff-crash.ll
+++ /dev/null
@@ -1,58 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s
-
-define i64 @strlen16_vec(ptr %s) {
-; CHECK-LABEL: strlen16_vec:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: li a3, -1
-; CHECK-NEXT: li a4, 16
-; CHECK-NEXT: j .LBB0_2
-; CHECK-NEXT: .LBB0_1: # %while.body
-; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: add a1, a6, a1
-; CHECK-NEXT: bne a5, a3, .LBB0_5
-; CHECK-NEXT: .LBB0_2: # %while.cond
-; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: bne a4, a2, .LBB0_5
-; CHECK-NEXT: # %bb.3: # %while.body
-; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma
-; CHECK-NEXT: vle16ff.v v8, (a0)
-; CHECK-NEXT: csrr a4, vl
-; CHECK-NEXT: vmseq.vi v8, v8, 0
-; CHECK-NEXT: vfirst.m a5, v8
-; CHECK-NEXT: mv a6, a4
-; CHECK-NEXT: beq a5, a3, .LBB0_1
-; CHECK-NEXT: # %bb.4: # %while.body
-; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT: mv a6, a5
-; CHECK-NEXT: j .LBB0_1
-; CHECK-NEXT: .LBB0_5: # %while.end
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: ret
-entry:
- br label %while.cond
-
-while.cond: ; preds = %while.body, %entry
- %new_vl.0 = phi i64 [ 16, %entry ], [ %2, %while.body ]
- %len.0 = phi i64 [ 0, %entry ], [ %len.1, %while.body ]
- %cmp = icmp eq i64 %new_vl.0, 16
- br i1 %cmp, label %while.body, label %while.end
-
-while.body: ; preds = %while.cond
- %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> poison, ptr %s, i64 16)
- %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 0
- %2 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
- %3 = tail call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> %1, i16 0, i64 %2)
- %4 = tail call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %3, i64 %2)
- %cmp1 = icmp eq i64 %4, -1
- %.13 = select i1 %cmp1, i64 %2, i64 %4
- %len.1 = add i64 %.13, %len.0
- br i1 %cmp1, label %while.cond, label %while.end
-
-while.end: ; preds = %while.body, %while.cond
- %len.2 = phi i64 [ %len.1, %while.body ], [ %len.0, %while.cond ]
- ret i64 %len.2
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 8b48dc43eca29..7f441ad303b91 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -722,3 +722,35 @@ define i64 @avl_undef2() {
%1 = tail call i64 @llvm.riscv.vsetvli(i64 poison, i64 2, i64 7)
ret i64 %1
}
+
+define i64 @vsetvli_vleff() {
+; CHECK-LABEL: vsetvli_vleff:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: .LBB37_1: # %while.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vsetivli zero, 0, e16, m1, tu, ma
+; CHECK-NEXT: vmv1r.v v9, v8
+; CHECK-NEXT: vle16ff.v v9, (zero)
+; CHECK-NEXT: csrr a0, vl
+; CHECK-NEXT: beqz a0, .LBB37_1
+; CHECK-NEXT: # %bb.2: # %while.end
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+entry:
+ br label %while.cond
+
+while.cond:
+ %new_vl.0 = phi i64 [ 0, %entry ], [ %1, %while.body ]
+ %cmp = icmp eq i64 %new_vl.0, 0
+ br i1 %cmp, label %while.body, label %while.end
+
+while.body:
+ %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
+ %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
+ br label %while.cond
+
+while.end:
+ ret i64 0
+}
>From ae439a6609dd69408a087dca5d4990517be56c81 Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Wed, 2 Jul 2025 08:32:04 +0000
Subject: [PATCH 3/4] Added MIR test
---
.../test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 6bd03eb0c2226..ef6abd9bf18f0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -68,6 +68,24 @@
ret <vscale x 1 x i64> %b
}
+ define i64 @vsetvli_vleff() {
+ entry:
+ br label %while.cond
+
+ while.cond: ; preds = %while.body, %entry
+ %new_vl.0 = phi i64 [ 0, %entry ], [ %1, %while.body ]
+ %cmp = icmp eq i64 %new_vl.0, 0
+ br i1 %cmp, label %while.body, label %while.end
+
+ while.body: ; preds = %while.cond
+ %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
+ %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
+ br label %while.cond
+
+ while.end: ; preds = %while.cond
+ ret i64 0
+ }
+
define void @vmv_v_i_different_lmuls() {
ret void
}
@@ -622,3 +640,75 @@ body: |
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
%v:vr = COPY $v8, implicit $vtype
%x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
+...
+---
+name: vsetvli_vleff
+alignment: 4
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+ - { id: 5, class: vr, preferred-register: '%7' }
+ - { id: 6, class: gpr, preferred-register: '' }
+ - { id: 7, class: vr, preferred-register: '%5' }
+ - { id: 8, class: vr, preferred-register: '' }
+ - { id: 9, class: gpr, preferred-register: '' }
+frameInfo:
+ maxAlignment: 1
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: vsetvli_vleff
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.while.cond:
+ ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK-NEXT: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BNE [[COPY]], $x0, %bb.3
+ ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.while.body:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: renamable $v9 = COPY renamable $v8, implicit $vtype
+ ; CHECK-NEXT: dead renamable $v9, $x0 = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = PseudoReadVL implicit $vl
+ ; CHECK-NEXT: PseudoBR %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.while.end:
+ ; CHECK-NEXT: $x10 = COPY $x0
+ ; CHECK-NEXT: PseudoRET implicit killed $x10
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+
+ %9:gpr = COPY $x0
+ renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
+
+ bb.1.while.cond:
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $v8
+
+ BNE %9, $x0, %bb.3
+ PseudoBR %bb.2
+
+ bb.2.while.body:
+ successors: %bb.1(0x80000000)
+ liveins: $v8
+
+ renamable $v9 = COPY renamable $v8
+ dead renamable $v9, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
+ PseudoBR %bb.1
+
+ bb.3.while.end:
+ $x10 = COPY $x0
+ PseudoRET implicit killed $x10
>From 5e89c268e8abcbbbec675cca93fd182f5e8ddaf9 Mon Sep 17 00:00:00 2001
From: sc-cluzze <d.marakulin at syntacore.com>
Date: Thu, 3 Jul 2025 13:23:31 +0000
Subject: [PATCH 4/4] Addressed comments
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 +-
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 14 +--
.../test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 105 ++++++------------
3 files changed, 42 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index bc4bf94d16042..dd002473a06e2 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1768,7 +1768,7 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
SlotIndex NewDefSI =
LIS->InsertMachineInstrInMaps(*ReadVLMI).getRegSlot();
LiveInterval &DefLI = LIS->getInterval(VLOutput);
- const auto *DefSeg = DefLI.getSegmentContaining(NewDefSI);
+ LiveRange::Segment *DefSeg = DefLI.getSegmentContaining(NewDefSI);
VNInfo *DefVNI = DefLI.getVNInfoAt(DefSeg->start);
DefLI.removeSegment(DefSeg->start, NewDefSI);
DefVNI->def = NewDefSI;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 7f441ad303b91..a61e56d7877b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -723,18 +723,18 @@ define i64 @avl_undef2() {
ret i64 %1
}
-define i64 @vsetvli_vleff() {
+define i64 @vsetvli_vleff(ptr %s, i64 %evl) {
; CHECK-LABEL: vsetvli_vleff:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB37_1: # %while.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetivli zero, 0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vle16ff.v v9, (zero)
-; CHECK-NEXT: csrr a0, vl
-; CHECK-NEXT: beqz a0, .LBB37_1
+; CHECK-NEXT: vle16ff.v v9, (a0)
+; CHECK-NEXT: csrr a2, vl
+; CHECK-NEXT: beqz a2, .LBB37_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
@@ -747,7 +747,7 @@ while.cond:
br i1 %cmp, label %while.body, label %while.end
while.body:
- %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
+ %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr %s, i64 %evl)
%1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
br label %while.cond
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index ef6abd9bf18f0..962fb1dcc485a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -68,24 +68,6 @@
ret <vscale x 1 x i64> %b
}
- define i64 @vsetvli_vleff() {
- entry:
- br label %while.cond
-
- while.cond: ; preds = %while.body, %entry
- %new_vl.0 = phi i64 [ 0, %entry ], [ %1, %while.body ]
- %cmp = icmp eq i64 %new_vl.0, 0
- br i1 %cmp, label %while.body, label %while.end
-
- while.body: ; preds = %while.cond
- %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
- %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
- br label %while.cond
-
- while.end: ; preds = %while.cond
- ret i64 0
- }
-
define void @vmv_v_i_different_lmuls() {
ret void
}
@@ -118,6 +100,18 @@
ret void
}
+ define i64 @vsetvli_vleff() {
+ bb0:
+ br i1 poison, label %bb1, label %bb2
+ bb1:
+ %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> zeroinitializer, ptr null, i64 0)
+ %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
+ br label %bb2
+ bb2:
+ %x8 = phi i64 [%1, %bb1], [0, %bb0]
+ ret i64 %x8
+ }
+
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, ptr nocapture, i64) #4
@@ -643,72 +637,41 @@ body: |
...
---
name: vsetvli_vleff
-alignment: 4
tracksRegLiveness: true
-registers:
- - { id: 0, class: gpr, preferred-register: '' }
- - { id: 1, class: gpr, preferred-register: '' }
- - { id: 2, class: gpr, preferred-register: '' }
- - { id: 3, class: gpr, preferred-register: '' }
- - { id: 4, class: gpr, preferred-register: '' }
- - { id: 5, class: vr, preferred-register: '%7' }
- - { id: 6, class: gpr, preferred-register: '' }
- - { id: 7, class: vr, preferred-register: '%5' }
- - { id: 8, class: vr, preferred-register: '' }
- - { id: 9, class: gpr, preferred-register: '' }
-frameInfo:
- maxAlignment: 1
-machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: vsetvli_vleff
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK: bb.0.bb0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.while.cond:
- ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- ; CHECK-NEXT: liveins: $v8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BNE [[COPY]], $x0, %bb.3
- ; CHECK-NEXT: PseudoBR %bb.2
+ ; CHECK-NEXT: BNE $x0, $x0, %bb.2
+ ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.while.body:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $v8
+ ; CHECK-NEXT: bb.1.bb1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: renamable $v9 = COPY renamable $v8, implicit $vtype
- ; CHECK-NEXT: dead renamable $v9, $x0 = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 136 /* e16, m1, tu, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead renamable $v8, $x0 = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from `ptr null`, align 2)
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = PseudoReadVL implicit $vl
- ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3.while.end:
- ; CHECK-NEXT: $x10 = COPY $x0
+ ; CHECK-NEXT: bb.2.bb2:
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit killed $x10
- bb.0.entry:
- successors: %bb.1(0x80000000)
+ bb.0.bb0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
%9:gpr = COPY $x0
- renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
-
- bb.1.while.cond:
- successors: %bb.2(0x7c000000), %bb.3(0x04000000)
- liveins: $v8
-
- BNE %9, $x0, %bb.3
- PseudoBR %bb.2
+ BNE $x0, $x0, %bb.2
+ PseudoBR %bb.1
- bb.2.while.body:
- successors: %bb.1(0x80000000)
- liveins: $v8
+ bb.1.bb1:
+ successors: %bb.2(0x80000000)
- renamable $v9 = COPY renamable $v8
- dead renamable $v9, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v9, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
- PseudoBR %bb.1
+ renamable $v8 = PseudoVMV_V_I_M1 undef renamable $v8, 0, -1, 4 /* e16 */, 0 /* tu, mu */
+ dead renamable $v8, %9:gpr = PseudoVLE16FF_V_M1 killed renamable $v8, $x0, 0, 4 /* e16 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from `ptr null`, align 2)
- bb.3.while.end:
- $x10 = COPY $x0
+ bb.2.bb2:
+ $x10 = COPY %9
PseudoRET implicit killed $x10
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