[llvm] c79fcfe - [DAG] combineVSelectWithAllOnesOrZeros - reusing existing VT. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 3 02:58:16 PDT 2025
Author: Simon Pilgrim
Date: 2025-07-03T10:57:55+01:00
New Revision: c79fcfee4125dd0ad50b441517c04c55000dc7e9
URL: https://github.com/llvm/llvm-project/commit/c79fcfee4125dd0ad50b441517c04c55000dc7e9
DIFF: https://github.com/llvm/llvm-project/commit/c79fcfee4125dd0ad50b441517c04c55000dc7e9.diff
LOG: [DAG] combineVSelectWithAllOnesOrZeros - reusing existing VT. NFC.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 45ddcb0db633b..586eb2f3cf45e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13074,12 +13074,11 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
const TargetLowering &TLI,
SelectionDAG &DAG,
const SDLoc &DL) {
- if (!TLI.isTypeLegal(TVal.getValueType()))
+ EVT VT = TVal.getValueType();
+ if (!TLI.isTypeLegal(VT))
return SDValue();
- EVT VT = TVal.getValueType();
EVT CondVT = Cond.getValueType();
-
assert(CondVT.isVector() && "Vector select expects a vector selector!");
bool IsTAllZero = ISD::isBuildVectorAllZeros(TVal.getNode());
@@ -13110,7 +13109,7 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
}
// To use the condition operand as a bitwise mask, it must have elements that
- // are the same size as the select elements. Ie, the condition operand must
+ // are the same size as the select elements. i.e, the condition operand must
// have already been promoted from the IR select condition type <N x i1>.
// Don't check if the types themselves are equal because that excludes
// vector floating-point selects.
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