[llvm] 032966f - [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 3 01:59:16 PDT 2025
Author: UmeshKalappa
Date: 2025-07-03T10:59:10+02:00
New Revision: 032966ff5679804e826b76beab6306e277ef8d33
URL: https://github.com/llvm/llvm-project/commit/032966ff5679804e826b76beab6306e277ef8d33
DIFF: https://github.com/llvm/llvm-project/commit/032966ff5679804e826b76beab6306e277ef8d33.diff
LOG: [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)
the extension enabled with xmipscbop.
Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System
Programmer’s Guide" for more info on the extension at
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
Added:
llvm/test/CodeGen/RISCV/xmips-cbop.ll
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Driver/riscv-cpus.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/MC/RISCV/xmips-invalid.s
llvm/test/MC/RISCV/xmips-valid.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 314fdad7e52e7..2a9d4f3f9d1ba 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -169,6 +169,7 @@
// CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
// CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
+// CHECK-NEXT: xmipscbop 1.0 'XMIPSCBOP' (MIPS Software Prefetch)
// CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3736e76ed06dd..d32d1c1a8183f 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -186,6 +186,9 @@
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc"
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+xmipscbop"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+xmipscmov"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+xmipslsp"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
// MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 81684ba30f12c..82114791b3c0c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -498,6 +498,9 @@ The current vendor extensions supported are:
``experimental-Xqcisync``
LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
+``Xmipscbop``
+ LLVM implements MIPS prefetch extension `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
+
``Xmipscmov``
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index bb0f9df2032fd..886486eef0a15 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -732,6 +732,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isUImm6() const { return isUImm<6>(); }
bool isUImm7() const { return isUImm<7>(); }
bool isUImm8() const { return isUImm<8>(); }
+ bool isUImm9() const { return isUImm<9>(); }
bool isUImm10() const { return isUImm<10>(); }
bool isUImm11() const { return isUImm<11>(); }
bool isUImm16() const { return isUImm<16>(); }
@@ -1527,6 +1528,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 8) - 8,
"immediate must be a multiple of 8 bytes in the range");
+ case Match_InvalidUImm9:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 9) - 1,
+ "immediate offset must be in the range");
case Match_InvalidBareSImm9Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 52061e96d0018..aa45e7eeca56f 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -790,6 +790,9 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXmipscmov32,
{RISCV::FeatureVendorXMIPSCMov},
"MIPS mips.ccmov"},
+ {DecoderTableXmipscbop32,
+ {RISCV::FeatureVendorXMIPSCBOP},
+ "MIPS mips.pref"},
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
// Standard Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d296f76ad10ca..e123ef45fa503 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -316,6 +316,7 @@ enum OperandType : unsigned {
OPERAND_UIMM8_LSB000,
OPERAND_UIMM8_GE32,
OPERAND_UIMM9_LSB000,
+ OPERAND_UIMM9,
OPERAND_UIMM10,
OPERAND_UIMM10_LSB00_NONZERO,
OPERAND_UIMM11,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6e103dd7d8c44..292f689e2dfb8 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1404,6 +1404,13 @@ def HasVendorXMIPSLSP
: Predicate<"Subtarget->hasVendorXMIPSLSP()">,
AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
"'Xmipslsp' (load and store pair instructions)">;
+def FeatureVendorXMIPSCBOP
+ : RISCVExtension<1, 0, "MIPS Software Prefetch">;
+def HasVendorXMIPSCBOP
+ : Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
+ "'Xmipscbop' (MIPS hardware prefetch)">;
+def NotHasVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
// WCH / Nanjing Qinheng Microelectronics Extension(s)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 29eac6317080f..1b748016a1928 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2921,6 +2921,33 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
return true;
}
+/// Similar to SelectAddrRegImm, except that the offset restricted for
+/// unsinged nine bits.
+bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
+ SDValue &Offset) {
+ if (SelectAddrFrameIndex(Addr, Base, Offset))
+ return true;
+
+ SDLoc DL(Addr);
+ MVT VT = Addr.getSimpleValueType();
+
+ if (CurDAG->isBaseWithConstantOffset(Addr)) {
+ int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+ if (isUInt<9>(CVal)) {
+ Base = Addr.getOperand(0);
+
+ if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
+ Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
+ return true;
+ }
+ }
+
+ Base = Addr;
+ Offset = CurDAG->getTargetConstant(0, DL, VT);
+ return true;
+}
+
/// Similar to SelectAddrRegImm, except that the least significant 5 bits of
/// Offset should be all zeros.
bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index cb63c21fd8fc9..65c2220e25822 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -47,6 +47,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
+ bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ea3fa253ae5c0..dac6ed6d40199 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -683,9 +683,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.is64Bit())
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
- if (Subtarget.hasStdExtZicbop()) {
+ if (Subtarget.hasVendorXMIPSCBOP())
+ setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
+ else if (Subtarget.hasStdExtZicbop())
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
- }
if (Subtarget.hasStdExtA()) {
setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
@@ -6613,6 +6614,17 @@ SDValue RISCVTargetLowering::lowerConstantFP(SDValue Op,
return DAG.getNode(ISD::FNEG, DL, VT, Const);
}
+static SDValue LowerPREFETCH(SDValue Op, const RISCVSubtarget &Subtarget,
+ SelectionDAG &DAG) {
+
+ unsigned IsData = Op.getConstantOperandVal(4);
+
+ // mips-p8700 we support data prefetch for now.
+ if (Subtarget.hasVendorXMIPSCBOP() && !IsData)
+ return Op.getOperand(0);
+ return Op;
+}
+
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDLoc dl(Op);
@@ -7178,6 +7190,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
switch (Op.getOpcode()) {
default:
report_fatal_error("unimplemented operand");
+ case ISD::PREFETCH:
+ return LowerPREFETCH(Op, Subtarget, DAG);
case ISD::ATOMIC_FENCE:
return LowerATOMIC_FENCE(Op, DAG, Subtarget);
case ISD::GlobalAddress:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9a36f1c694faf..2723229859a55 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2805,7 +2805,8 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_UIMM(6)
CASE_OPERAND_UIMM(7)
CASE_OPERAND_UIMM(8)
- CASE_OPERAND_UIMM(10)
+ CASE_OPERAND_UIMM(9)
+ CASE_OPERAND_UIMM(10)
CASE_OPERAND_UIMM(12)
CASE_OPERAND_UIMM(16)
CASE_OPERAND_UIMM(20)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
index ff751994b89b9..0c8487c2f5dbe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -29,6 +29,12 @@ def uimm7_lsb000 : RISCVOp,
}];
}
+// A 9-bit unsigned offset
+def uimm9 : RISCVUImmOp<9>;
+
+// Custom prefetch ADDR selector
+def AddrRegImm9 : ComplexPattern<iPTR, 2, "SelectAddrRegImm9">;
+
//===----------------------------------------------------------------------===//
// MIPS custom instruction formats
//===----------------------------------------------------------------------===//
@@ -103,9 +109,41 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
let Inst{6-0} = OPC_CUSTOM_0.Value;
}
+// Prefetch format.
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
+class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+ bits<9> imm9;
+ bits<5> rs1;
+ bits<5> hint;
+
+ let Inst{31-29} = 0b000;
+ let Inst{28-20} = imm9;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b000;
+ let Inst{11-7} = hint;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
//===----------------------------------------------------------------------===//
// MIPS extensions
//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
+ def MIPS_PREFETCH : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
+ "mips.pref", "$hint, ${imm9}(${rs1})">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorXMIPSCBOP] in {
+ // Prefetch Data Write.
+ def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
+ (i32 1), timm, (i32 1)),
+ (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
+ // Prefetch Data Read.
+ def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
+ (i32 0), timm, (i32 1)),
+ (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
+}
let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
DecoderNamespace = "Xmipscmov" in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index e44bdcb4e2f0f..878b85b141578 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -57,7 +57,7 @@ let Predicates = [HasStdExtZicboz] in {
def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
} // Predicates = [HasStdExtZicboz]
-let Predicates = [HasStdExtZicbop] in {
+let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
@@ -69,7 +69,7 @@ def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
def AddrRegImmLsb00000 : ComplexPattern<iPTR, 2, "SelectAddrRegImmLsb00000">;
-let Predicates = [HasStdExtZicbop] in {
+let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
timm, timm, (i32 0)),
(PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>;
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 57b415dc713ac..03214fe8239ce 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -120,7 +120,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
FeatureStdExtZifencei,
FeatureStdExtZicsr,
FeatureVendorXMIPSCMov,
- FeatureVendorXMIPSLSP],
+ FeatureVendorXMIPSLSP,
+ FeatureVendorXMIPSCBOP],
[TuneMIPSP8700]>;
def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index af2e31e5d5331..ed8753eee130a 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -183,6 +183,7 @@
; CHECK-NEXT: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate).
; CHECK-NEXT: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store).
; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).
+; CHECK-NEXT: xmipscbop - 'XMIPSCBOP' (MIPS Software Prefetch).
; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
new file mode 100644
index 0000000000000..cbbd1de13192c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
+; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
+
+define void @prefetch_data_read(ptr noundef %ptr) nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_data_read:
+; RV32XMIPSPREFETCH: # %bb.0: # %entry
+; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 1(a0)
+; RV32XMIPSPREFETCH-NEXT: ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_data_read:
+; RV64XMIPSPREFETCH: # %bb.0: # %entry
+; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 1(a0)
+; RV64XMIPSPREFETCH-NEXT: ret
+entry:
+ %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 1
+ tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 1)
+ ret void
+}
+
+define void @prefetch_data_write(ptr noundef %ptr) nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_data_write:
+; RV32XMIPSPREFETCH: # %bb.0:
+; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 512
+; RV32XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
+; RV32XMIPSPREFETCH-NEXT: ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_data_write:
+; RV64XMIPSPREFETCH: # %bb.0:
+; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 512
+; RV64XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
+; RV64XMIPSPREFETCH-NEXT: ret
+ %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
+ tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 1, i32 0, i32 1)
+ ret void
+}
+
+define void @prefetch_inst_read(ptr noundef %ptr) nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_inst_read:
+; RV32XMIPSPREFETCH: # %bb.0:
+; RV32XMIPSPREFETCH-NEXT: ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_inst_read:
+; RV64XMIPSPREFETCH: # %bb.0:
+; RV64XMIPSPREFETCH-NEXT: ret
+ %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
+ tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0)
+ ret void
+}
diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
index b3834e7b3407f..a17d2e347f8d9 100644
--- a/llvm/test/MC/RISCV/xmips-invalid.s
+++ b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,5 +1,14 @@
# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
-# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+Xmipscbop < %s 2>&1 | FileCheck %s
+
+mips.pref 8, 512(a0)
+# CHECK: error: immediate offset must be in the range [0, 511]
+
+mips.pref 8
+# CHECK: error: too few operands for instruction
+
+mips.pref 8, 511(a0)
+# CHECK-FEATURE: error: instruction requires the following: 'Xmipscbop' (MIPS hardware prefetch)
mips.ccmov x0, x1, 0x10
# CHECK: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s
index 9f31e4fa2038c..c5755ee81b499 100644
--- a/llvm/test/MC/RISCV/xmips-valid.s
+++ b/llvm/test/MC/RISCV/xmips-valid.s
@@ -1,9 +1,21 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s \
-# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop < %s \
+# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+# CHECK-INST: mips.pref 8, 511(a0)
+# CHECK-ENC: encoding: [0x0b,0x04,0xf5,0x1f]
+mips.pref 8, 511(a0)
+
+# CHECK-DIS: mips.pref 0x8, 0x1ff(a0)
+
+# CHECK-INST: mips.pref 9, 0(a0)
+# CHECK-ENC: encoding: [0x8b,0x04,0x05,0x00]
+mips.pref 9, 0(a0)
+
+# CHECK-DIS: mips.pref 0x9, 0x0(a0)
+
# CHECK-INST: mips.ccmov s0, s1, s2, s3
# CHECK-ENC: encoding: [0x0b,0x34,0x99,0x9e]
mips.ccmov s0, s1, s2, s3
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 66e335a33a3f7..55314d6261fdf 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1140,6 +1140,7 @@ R"(All available -march extensions for RISC-V
xcvmac 1.0
xcvmem 1.0
xcvsimd 1.0
+ xmipscbop 1.0
xmipscmov 1.0
xmipslsp 1.0
xsfcease 1.0
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