[llvm] 31e85f9 - MCAsmBackend: Make some target overrides out-of-line
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 2 21:48:39 PDT 2025
Author: Fangrui Song
Date: 2025-07-02T21:48:34-07:00
New Revision: 31e85f987d5834ba5ca301eb1d1bbb835804cf35
URL: https://github.com/llvm/llvm-project/commit/31e85f987d5834ba5ca301eb1d1bbb835804cf35
DIFF: https://github.com/llvm/llvm-project/commit/31e85f987d5834ba5ca301eb1d1bbb835804cf35.diff
LOG: MCAsmBackend: Make some target overrides out-of-line
To align with the majority of targets where these overrides are
out-of-line. The consistency helps the pending change that
merges addReloc and applyFixup.
Added:
Modified:
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 45bb82c945a7a..509b02927686a 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -404,131 +404,9 @@ class HexagonAsmBackend : public MCAsmBackend {
llvm_unreachable(errStr.str().c_str());
}
- /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
- /// data fragment, at the offset specified by the fixup and following the
- /// fixup kind as appropriate.
- void applyFixup(const MCFragment &, const MCFixup &Fixup,
- const MCValue &Target, MutableArrayRef<char> Data,
- uint64_t FixupValue, bool IsResolved) override {
-
- // When FixupValue is 0 the relocation is external and there
- // is nothing for us to do.
- if (!FixupValue) return;
-
- MCFixupKind Kind = Fixup.getKind();
- uint64_t Value;
- uint32_t InstMask;
- uint32_t Reloc;
-
- // LLVM gives us an encoded value, we have to convert it back
- // to a real offset before we can use it.
- uint32_t Offset = Fixup.getOffset();
- unsigned NumBytes = getFixupKindNumBytes(Kind);
- assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
- char *InstAddr = Data.data() + Offset;
-
- Value = adjustFixupValue(Kind, FixupValue);
- if(!Value)
- return;
- int sValue = (int)Value;
-
- switch((unsigned)Kind) {
- default:
- return;
-
- case fixup_Hexagon_B7_PCREL:
- if (!(isIntN(7, sValue)))
- HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
- [[fallthrough]];
- case fixup_Hexagon_B7_PCREL_X:
- InstMask = 0x00001f18; // Word32_B7
- Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
- ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
- break;
-
- case fixup_Hexagon_B9_PCREL:
- if (!(isIntN(9, sValue)))
- HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
- [[fallthrough]];
- case fixup_Hexagon_B9_PCREL_X:
- InstMask = 0x003000fe; // Word32_B9
- Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
- ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
- break;
-
- // Since the existing branches that use this relocation cannot be
- // extended, they should only be fixed up if the target is within range.
- case fixup_Hexagon_B13_PCREL:
- if (!(isIntN(13, sValue)))
- HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
- [[fallthrough]];
- case fixup_Hexagon_B13_PCREL_X:
- InstMask = 0x00202ffe; // Word32_B13
- Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
- (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
- ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
- break;
-
- case fixup_Hexagon_B15_PCREL:
- if (!(isIntN(15, sValue)))
- HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
- [[fallthrough]];
- case fixup_Hexagon_B15_PCREL_X:
- InstMask = 0x00df20fe; // Word32_B15
- Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
- (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
- (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
- ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
- break;
-
- case fixup_Hexagon_B22_PCREL:
- if (!(isIntN(22, sValue)))
- HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
- [[fallthrough]];
- case fixup_Hexagon_B22_PCREL_X:
- InstMask = 0x01ff3ffe; // Word32_B22
- Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
- ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
- break;
-
- case fixup_Hexagon_B32_PCREL_X:
- InstMask = 0x0fff3fff; // Word32_X26
- Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
- (Value & 0x3fff); // Value 13-0 = Target 13-0
- break;
-
- case FK_Data_1:
- case FK_Data_2:
- case FK_Data_4:
- case fixup_Hexagon_32:
- InstMask = 0xffffffff; // Word32
- Reloc = Value;
- break;
- }
-
- LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
- << (unsigned)Kind << ")\n");
- LLVM_DEBUG(
- uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
- (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
- dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
- dbgs().write_hex(FixupValue)
- << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
- dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
-
- // For each byte of the fragment that the fixup touches, mask in the
- // bits from the fixup value. The Value has been "split up" into the
- // appropriate bitfields above.
- for (unsigned i = 0; i < NumBytes; i++){
- InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
- InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
- }
-
- LLVM_DEBUG(uint32_t NewData = 0;
- for (unsigned i = 0; i < NumBytes; i++) NewData |=
- (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
- dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
- }
+ void applyFixup(const MCFragment &, const MCFixup &, const MCValue &,
+ MutableArrayRef<char> Data, uint64_t FixupValue,
+ bool IsResolved) override;
bool isInstRelaxable(MCInst const &HMI) const {
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
@@ -775,6 +653,130 @@ class HexagonAsmBackend : public MCAsmBackend {
} // namespace
+void HexagonAsmBackend::applyFixup(const MCFragment &, const MCFixup &Fixup,
+ const MCValue &Target,
+ MutableArrayRef<char> Data,
+ uint64_t FixupValue, bool IsResolved) {
+ // When FixupValue is 0 the relocation is external and there
+ // is nothing for us to do.
+ if (!FixupValue)
+ return;
+
+ MCFixupKind Kind = Fixup.getKind();
+ uint64_t Value;
+ uint32_t InstMask;
+ uint32_t Reloc;
+
+ // LLVM gives us an encoded value, we have to convert it back
+ // to a real offset before we can use it.
+ uint32_t Offset = Fixup.getOffset();
+ unsigned NumBytes = getFixupKindNumBytes(Kind);
+ assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
+ char *InstAddr = Data.data() + Offset;
+
+ Value = adjustFixupValue(Kind, FixupValue);
+ if (!Value)
+ return;
+ int sValue = (int)Value;
+
+ switch ((unsigned)Kind) {
+ default:
+ return;
+
+ case fixup_Hexagon_B7_PCREL:
+ if (!(isIntN(7, sValue)))
+ HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
+ [[fallthrough]];
+ case fixup_Hexagon_B7_PCREL_X:
+ InstMask = 0x00001f18; // Word32_B7
+ Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
+ ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
+ break;
+
+ case fixup_Hexagon_B9_PCREL:
+ if (!(isIntN(9, sValue)))
+ HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
+ [[fallthrough]];
+ case fixup_Hexagon_B9_PCREL_X:
+ InstMask = 0x003000fe; // Word32_B9
+ Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
+ ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
+ break;
+
+ // Since the existing branches that use this relocation cannot be
+ // extended, they should only be fixed up if the target is within range.
+ case fixup_Hexagon_B13_PCREL:
+ if (!(isIntN(13, sValue)))
+ HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
+ [[fallthrough]];
+ case fixup_Hexagon_B13_PCREL_X:
+ InstMask = 0x00202ffe; // Word32_B13
+ Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
+ (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
+ ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
+ break;
+
+ case fixup_Hexagon_B15_PCREL:
+ if (!(isIntN(15, sValue)))
+ HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
+ [[fallthrough]];
+ case fixup_Hexagon_B15_PCREL_X:
+ InstMask = 0x00df20fe; // Word32_B15
+ Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
+ (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
+ (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
+ ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
+ break;
+
+ case fixup_Hexagon_B22_PCREL:
+ if (!(isIntN(22, sValue)))
+ HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
+ [[fallthrough]];
+ case fixup_Hexagon_B22_PCREL_X:
+ InstMask = 0x01ff3ffe; // Word32_B22
+ Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
+ ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
+ break;
+
+ case fixup_Hexagon_B32_PCREL_X:
+ InstMask = 0x0fff3fff; // Word32_X26
+ Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
+ (Value & 0x3fff); // Value 13-0 = Target 13-0
+ break;
+
+ case FK_Data_1:
+ case FK_Data_2:
+ case FK_Data_4:
+ case fixup_Hexagon_32:
+ InstMask = 0xffffffff; // Word32
+ Reloc = Value;
+ break;
+ }
+
+ LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
+ << (unsigned)Kind << ")\n");
+ LLVM_DEBUG(
+ uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
+ (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
+ dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
+ dbgs().write_hex(FixupValue)
+ << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
+ dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
+
+ // For each byte of the fragment that the fixup touches, mask in the
+ // bits from the fixup value. The Value has been "split up" into the
+ // appropriate bitfields above.
+ for (unsigned i = 0; i < NumBytes; i++) {
+ InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
+ InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
+ }
+
+ LLVM_DEBUG(uint32_t NewData = 0;
+ for (unsigned i = 0; i < NumBytes; i++) NewData |=
+ (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
+ dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
+}
+
// MCAsmBackend
MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
index 20a37302a5e1c..48e130f99a60c 100644
--- a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
+++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
@@ -52,23 +52,9 @@ class M68kAsmBackend : public MCAsmBackend {
.CasesLower("m68020", "m68030", "m68040", true)
.Default(false)) {}
- void applyFixup(const MCFragment &, const MCFixup &Fixup, const MCValue &,
- MutableArrayRef<char> Data, uint64_t Value, bool) override {
- unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
-
- assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!");
- // Check that uppper bits are either all zeros or all ones.
- // Specifically ignore overflow/underflow as long as the leakage is
- // limited to the lower bits. This is to remain compatible with
- // other assemblers.
- assert(isIntN(Size * 8 + 1, static_cast<int64_t>(Value)) &&
- "Value does not fit in the Fixup field");
-
- // Write in Big Endian
- for (unsigned i = 0; i != Size; ++i)
- Data[Fixup.getOffset() + i] =
- uint8_t(static_cast<int64_t>(Value) >> ((Size - i - 1) * 8));
- }
+ void applyFixup(const MCFragment &, const MCFixup &, const MCValue &,
+ MutableArrayRef<char> Data, uint64_t Value,
+ bool IsResolved) override;
bool mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const override;
@@ -91,6 +77,25 @@ class M68kAsmBackend : public MCAsmBackend {
};
} // end anonymous namespace
+void M68kAsmBackend::applyFixup(const MCFragment &, const MCFixup &Fixup,
+ const MCValue &, MutableArrayRef<char> Data,
+ uint64_t Value, bool) {
+ unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
+
+ assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!");
+ // Check that uppper bits are either all zeros or all ones.
+ // Specifically ignore overflow/underflow as long as the leakage is
+ // limited to the lower bits. This is to remain compatible with
+ // other assemblers.
+ assert(isIntN(Size * 8 + 1, static_cast<int64_t>(Value)) &&
+ "Value does not fit in the Fixup field");
+
+ // Write in Big Endian
+ for (unsigned i = 0; i != Size; ++i)
+ Data[Fixup.getOffset() + i] =
+ uint8_t(static_cast<int64_t>(Value) >> ((Size - i - 1) * 8));
+}
+
/// cc—Carry clear GE—Greater than or equal
/// LS—Lower or same PL—Plus
/// CS—Carry set GT—Greater than
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index 658089f9582d6..a9e3ed79d6a56 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -91,48 +91,7 @@ class PPCAsmBackend : public MCAsmBackend {
: llvm::endianness::big),
TT(TT) {}
- MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
- const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
- // name offset bits flags
- { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_br24abs", 6, 24, 0 },
- { "fixup_ppc_brcond14abs", 16, 14, 0 },
- { "fixup_ppc_half16", 0, 16, 0 },
- { "fixup_ppc_half16ds", 0, 14, 0 },
- { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_imm34", 0, 34, 0 },
- { "fixup_ppc_nofixup", 0, 0, 0 }
- };
- const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
- // name offset bits flags
- { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_br24abs", 2, 24, 0 },
- { "fixup_ppc_brcond14abs", 2, 14, 0 },
- { "fixup_ppc_half16", 0, 16, 0 },
- { "fixup_ppc_half16ds", 2, 14, 0 },
- { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_imm34", 0, 34, 0 },
- { "fixup_ppc_nofixup", 0, 0, 0 }
- };
-
- // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
- // do not require any extra processing.
- if (mc::isRelocation(Kind))
- return MCAsmBackend::getFixupKindInfo(FK_NONE);
-
- if (Kind < FirstTargetFixupKind)
- return MCAsmBackend::getFixupKindInfo(Kind);
-
- assert(Kind - FirstTargetFixupKind < PPC::NumTargetFixupKinds &&
- "Invalid kind!");
- return (Endian == llvm::endianness::little
- ? InfosLE
- : InfosBE)[Kind - FirstTargetFixupKind];
- }
+ MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
bool addReloc(const MCFragment &F, const MCFixup &Fixup,
const MCValue &TargetVal, uint64_t &FixedValue,
@@ -147,25 +106,7 @@ class PPCAsmBackend : public MCAsmBackend {
void applyFixup(const MCFragment &, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
- uint64_t Value, bool IsResolved) override {
- MCFixupKind Kind = Fixup.getKind();
- if (mc::isRelocation(Kind))
- return;
- Value = adjustFixupValue(Kind, Value);
- if (!Value) return; // Doesn't change encoding.
-
- unsigned Offset = Fixup.getOffset();
- unsigned NumBytes = getFixupKindNumBytes(Kind);
-
- // For each byte of the fragment that the fixup touches, mask in the bits
- // from the fixup value. The Value has been "split up" into the appropriate
- // bitfields above.
- for (unsigned i = 0; i != NumBytes; ++i) {
- unsigned Idx =
- Endian == llvm::endianness::little ? i : (NumBytes - 1 - i);
- Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
- }
- }
+ uint64_t Value, bool IsResolved) override;
bool shouldForceRelocation(const MCFixup &Fixup,
const MCValue &Target) override {
@@ -219,6 +160,69 @@ class PPCAsmBackend : public MCAsmBackend {
};
} // end anonymous namespace
+MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+ const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
+ // name offset bits flags
+ {"fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24abs", 6, 24, 0},
+ {"fixup_ppc_brcond14abs", 16, 14, 0},
+ {"fixup_ppc_half16", 0, 16, 0},
+ {"fixup_ppc_half16ds", 0, 14, 0},
+ {"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_imm34", 0, 34, 0},
+ {"fixup_ppc_nofixup", 0, 0, 0}};
+ const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
+ // name offset bits flags
+ {"fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_br24abs", 2, 24, 0},
+ {"fixup_ppc_brcond14abs", 2, 14, 0},
+ {"fixup_ppc_half16", 0, 16, 0},
+ {"fixup_ppc_half16ds", 2, 14, 0},
+ {"fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel},
+ {"fixup_ppc_imm34", 0, 34, 0},
+ {"fixup_ppc_nofixup", 0, 0, 0}};
+
+ // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
+ // do not require any extra processing.
+ if (mc::isRelocation(Kind))
+ return MCAsmBackend::getFixupKindInfo(FK_NONE);
+
+ if (Kind < FirstTargetFixupKind)
+ return MCAsmBackend::getFixupKindInfo(Kind);
+
+ assert(Kind - FirstTargetFixupKind < PPC::NumTargetFixupKinds &&
+ "Invalid kind!");
+ return (Endian == llvm::endianness::little
+ ? InfosLE
+ : InfosBE)[Kind - FirstTargetFixupKind];
+}
+
+void PPCAsmBackend::applyFixup(const MCFragment &, const MCFixup &Fixup,
+ const MCValue &Target,
+ MutableArrayRef<char> Data, uint64_t Value,
+ bool IsResolved) {
+ MCFixupKind Kind = Fixup.getKind();
+ if (mc::isRelocation(Kind))
+ return;
+ Value = adjustFixupValue(Kind, Value);
+ if (!Value)
+ return; // Doesn't change encoding.
+
+ unsigned Offset = Fixup.getOffset();
+ unsigned NumBytes = getFixupKindNumBytes(Kind);
+
+ // For each byte of the fragment that the fixup touches, mask in the bits
+ // from the fixup value. The Value has been "split up" into the appropriate
+ // bitfields above.
+ for (unsigned i = 0; i != NumBytes; ++i) {
+ unsigned Idx = Endian == llvm::endianness::little ? i : (NumBytes - 1 - i);
+ Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
+ }
+}
// FIXME: This should be in a separate file.
namespace {
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
index 9a23a0e09f164..41c6b49e8ed1a 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
@@ -135,6 +135,10 @@ class VEAsmBackend : public MCAsmBackend {
}
}
+ void applyFixup(const MCFragment &, const MCFixup &, const MCValue &,
+ MutableArrayRef<char>, uint64_t Value,
+ bool IsResolved) override;
+
bool mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const override {
// Not implemented yet. For example, if we have a branch with
@@ -202,6 +206,30 @@ class ELFVEAsmBackend : public VEAsmBackend {
};
} // end anonymous namespace
+void VEAsmBackend::applyFixup(const MCFragment &, const MCFixup &Fixup,
+ const MCValue &Target, MutableArrayRef<char> Data,
+ uint64_t Value, bool IsResolved) {
+ Value = adjustFixupValue(Fixup.getKind(), Value);
+ if (!Value)
+ return; // Doesn't change encoding.
+
+ MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
+
+ // Shift the value into position.
+ Value <<= Info.TargetOffset;
+
+ unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
+ unsigned Offset = Fixup.getOffset();
+ assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
+ // For each byte of the fragment that the fixup touches, mask in the bits
+ // from the fixup value. The Value has been "split up" into the
+ // appropriate bitfields above.
+ for (unsigned i = 0; i != NumBytes; ++i) {
+ unsigned Idx = Endian == llvm::endianness::little ? i : (NumBytes - 1) - i;
+ Data[Offset + Idx] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
+ }
+}
+
MCAsmBackend *llvm::createVEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
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