[llvm] [NFC][TableGen] Rename `CodeGenTarget` instruction accessors (PR #146767)
Rahul Joshi via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 2 12:59:19 PDT 2025
https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/146767
Rename `getXYZInstructionsByEnumValue()` to just `getXYZInstructions` and drop the `ByEnumValue` in the name.
>From 03e34d1f3eab3a394310b314b2445407883fc892 Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Wed, 2 Jul 2025 12:56:39 -0700
Subject: [PATCH] [NFC][TableGen] Rename `CodeGenTarget` instruction accessors
Rename `getXYZInstructionsByEnumValue()` to just `getXYZInstructions`
and drop the `ByEnumValue` in the name.
---
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
llvm/utils/TableGen/AsmWriterEmitter.cpp | 2 +-
llvm/utils/TableGen/CodeEmitterGen.cpp | 2 +-
llvm/utils/TableGen/CodeGenMapTable.cpp | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.cpp | 3 +--
.../utils/TableGen/Common/CodeGenSchedule.cpp | 14 +++++------
llvm/utils/TableGen/Common/CodeGenTarget.cpp | 2 +-
llvm/utils/TableGen/Common/CodeGenTarget.h | 25 ++++++++-----------
.../GlobalISel/GlobalISelMatchTable.cpp | 2 +-
.../TableGen/Common/VarLenCodeEmitterGen.cpp | 2 +-
llvm/utils/TableGen/DecoderEmitter.cpp | 2 +-
llvm/utils/TableGen/DisassemblerEmitter.cpp | 5 ++--
llvm/utils/TableGen/InstrDocsEmitter.cpp | 2 +-
llvm/utils/TableGen/InstrInfoEmitter.cpp | 10 ++++----
llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 2 +-
.../utils/TableGen/X86InstrMappingEmitter.cpp | 3 +--
llvm/utils/TableGen/X86MnemonicTables.cpp | 2 +-
17 files changed, 38 insertions(+), 44 deletions(-)
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 5a83c885c603d..6dec4110decbe 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1541,7 +1541,7 @@ void AsmMatcherInfo::buildInfo() {
Variant.Name = AsmVariant->getValueAsString("Name");
Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
- for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *CGI : Target.getInstructions()) {
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instructions we consider.
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index a3ea0f5e32e90..cbe645778fa3f 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -1314,7 +1314,7 @@ AsmWriterEmitter::AsmWriterEmitter(const RecordKeeper &R)
unsigned Variant = AsmWriter->getValueAsInt("Variant");
// Get the instruction numbering.
- NumberedInstructions = Target.getInstructionsByEnumValue();
+ NumberedInstructions = Target.getInstructions();
for (const auto &[Idx, I] : enumerate(NumberedInstructions)) {
if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 14dffb438fcba..3ab6f40a6deec 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -475,7 +475,7 @@ void CodeEmitterGen::run(raw_ostream &O) {
Target.reverseBitsForLittleEndianEncoding();
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
- Target.getInstructionsByEnumValue();
+ Target.getInstructions();
if (Target.hasVariableLengthEncodings()) {
emitVarLenCodeEmitter(Records, O);
diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp
index eccd1aff422d0..90f0a2ac8c268 100644
--- a/llvm/utils/TableGen/CodeGenMapTable.cpp
+++ b/llvm/utils/TableGen/CodeGenMapTable.cpp
@@ -358,7 +358,7 @@ const Record *MapTableEmitter::getInstrForColumn(const Record *KeyInstr,
unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) {
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
- Target.getInstructionsByEnumValue();
+ Target.getInstructions();
StringRef Namespace = Target.getInstNamespace();
ArrayRef<const ListInit *> ValueCols = InstrMapDesc.getValueCols();
unsigned NumCol = ValueCols.size();
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 86be0d12d7b8a..168240626dedf 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4122,8 +4122,7 @@ void CodeGenDAGPatterns::AddPatternToMatch(TreePattern *Pattern,
}
void CodeGenDAGPatterns::InferInstructionFlags() {
- ArrayRef<const CodeGenInstruction *> Instructions =
- Target.getInstructionsByEnumValue();
+ ArrayRef<const CodeGenInstruction *> Instructions = Target.getInstructions();
unsigned Errors = 0;
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 35c1ffb78ce8e..50346c29e8862 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -78,11 +78,11 @@ struct InstRegexOp : public SetTheory::Operator {
void apply(SetTheory &ST, const DagInit *Expr, SetTheory::RecSet &Elts,
ArrayRef<SMLoc> Loc) override {
ArrayRef<const CodeGenInstruction *> Generics =
- Target.getGenericInstructionsByEnumValue();
+ Target.getGenericInstructions();
ArrayRef<const CodeGenInstruction *> Pseudos =
- Target.getTargetPseudoInstructionsByEnumValue();
+ Target.getTargetPseudoInstructions();
ArrayRef<const CodeGenInstruction *> NonPseudos =
- Target.getTargetNonPseudoInstructionsByEnumValue();
+ Target.getTargetNonPseudoInstructions();
for (const Init *Arg : Expr->getArgs()) {
const StringInit *SI = dyn_cast<StringInit>(Arg);
@@ -587,7 +587,7 @@ void CodeGenSchedModels::collectSchedRW() {
// Find all SchedReadWrites referenced by instruction defs.
ConstRecVec SWDefs, SRDefs;
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
const Record *SchedDef = Inst->TheDef;
if (SchedDef->isValueUnset("SchedRW"))
continue;
@@ -836,7 +836,7 @@ void CodeGenSchedModels::collectSchedClasses() {
// Create a SchedClass for each unique combination of itinerary class and
// SchedRW list.
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
const Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
IdxVec Writes, Reads;
if (!Inst->TheDef->isValueUnset("SchedRW"))
@@ -861,7 +861,7 @@ void CodeGenSchedModels::collectSchedClasses() {
LLVM_DEBUG(
dbgs()
<< "\n+++ ITINERARIES and/or MACHINE MODELS (collectSchedClasses) +++\n");
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
StringRef InstName = Inst->TheDef->getName();
unsigned SCIdx = getSchedClassIdx(*Inst);
if (!SCIdx) {
@@ -1922,7 +1922,7 @@ void CodeGenSchedModels::checkCompleteness() {
const bool HasItineraries = ProcModel.hasItineraries();
if (!ProcModel.ModelDef->getValueAsBit("CompleteModel"))
continue;
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
if (Inst->hasNoSchedulingInfo)
continue;
if (ProcModel.isUnsupported(*Inst))
diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
index f8da985d45bed..a9002c5860fa3 100644
--- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
@@ -88,7 +88,7 @@ StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
/// namespace. The namespace is cached because it is requested multiple times.
StringRef CodeGenTarget::getInstNamespace() const {
if (InstNamespace.empty()) {
- for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : getInstructions()) {
// We are not interested in the "TargetOpcode" namespace.
if (Inst->Namespace != "TargetOpcode") {
InstNamespace = Inst->Namespace;
diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h
index 191647c114791..ac138344c83c6 100644
--- a/llvm/utils/TableGen/Common/CodeGenTarget.h
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.h
@@ -176,31 +176,28 @@ class CodeGenTarget {
/// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
/// - pseudo instructions in lexicographical order sorted by name;
/// - other instructions in lexicographical order sorted by name.
- ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
+ ArrayRef<const CodeGenInstruction *> getInstructions() const {
if (InstrsByEnum.empty())
ComputeInstrsByEnum();
return InstrsByEnum;
}
- // Functions that return various slices of `getInstructionsByEnumValue`.
- ArrayRef<const CodeGenInstruction *>
- getGenericInstructionsByEnumValue() const {
- return getInstructionsByEnumValue().take_front(getNumFixedInstructions());
+ // Functions that return various slices of `getInstructions`, ordered by
+ // their enum values.
+ ArrayRef<const CodeGenInstruction *> getGenericInstructions() const {
+ return getInstructions().take_front(getNumFixedInstructions());
}
- ArrayRef<const CodeGenInstruction *>
- getTargetInstructionsByEnumValue() const {
- return getInstructionsByEnumValue().drop_front(getNumFixedInstructions());
+ ArrayRef<const CodeGenInstruction *> getTargetInstructions() const {
+ return getInstructions().drop_front(getNumFixedInstructions());
}
- ArrayRef<const CodeGenInstruction *>
- getTargetPseudoInstructionsByEnumValue() const {
- return getTargetInstructionsByEnumValue().take_front(NumPseudoInstructions);
+ ArrayRef<const CodeGenInstruction *> getTargetPseudoInstructions() const {
+ return getTargetInstructions().take_front(NumPseudoInstructions);
}
- ArrayRef<const CodeGenInstruction *>
- getTargetNonPseudoInstructionsByEnumValue() const {
- return getTargetInstructionsByEnumValue().drop_front(NumPseudoInstructions);
+ ArrayRef<const CodeGenInstruction *> getTargetNonPseudoInstructions() const {
+ return getTargetInstructions().drop_front(NumPseudoInstructions);
}
/// Return the integer enum value corresponding to this instruction record.
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 327ac5f87777b..70141ba738bdb 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -1448,7 +1448,7 @@ void InstructionOpcodeMatcher::initOpcodeValuesMap(
const CodeGenTarget &Target) {
OpcodeValues.clear();
- for (const CodeGenInstruction *I : Target.getInstructionsByEnumValue())
+ for (const CodeGenInstruction *I : Target.getInstructions())
OpcodeValues[I] = Target.getInstrIntValue(I->TheDef);
}
diff --git a/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
index e5e03b8bd8bd2..77a2ae60ad6f9 100644
--- a/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
@@ -226,7 +226,7 @@ void VarLenInst::buildRec(const DagInit *DI) {
void VarLenCodeEmitterGen::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
- auto NumberedInstructions = Target.getInstructionsByEnumValue();
+ auto NumberedInstructions = Target.getInstructions();
for (const CodeGenInstruction *CGI : NumberedInstructions) {
const Record *R = CGI->TheDef;
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index d582309a6fd4a..a50fd06435a10 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -2572,7 +2572,7 @@ namespace {
if (HwModeNames.empty())
HwModeNames.push_back("");
- const auto &NumberedInstructions = Target.getInstructionsByEnumValue();
+ const auto &NumberedInstructions = Target.getInstructions();
NumberedEncodings.reserve(NumberedInstructions.size());
for (const auto &NumberedInstruction : NumberedInstructions) {
const Record *InstDef = NumberedInstruction->TheDef;
diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp
index 70d835e699ffe..15a11a3a99406 100644
--- a/llvm/utils/TableGen/DisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp
@@ -103,8 +103,7 @@ static void emitDisassembler(const RecordKeeper &Records, raw_ostream &OS) {
if (Target.getName() == "X86") {
DisassemblerTables Tables;
- for (const auto &[Idx, NumberedInst] :
- enumerate(Target.getInstructionsByEnumValue()))
+ for (const auto &[Idx, NumberedInst] : enumerate(Target.getInstructions()))
RecognizableInstr::processInstr(Tables, *NumberedInst, Idx);
if (Tables.hasConflicts()) {
@@ -120,7 +119,7 @@ static void emitDisassembler(const RecordKeeper &Records, raw_ostream &OS) {
// below (which depends on a Size table-gen Record), and also uses a custom
// disassembler.
if (Target.getName() == "WebAssembly") {
- emitWebAssemblyDisassemblerTables(OS, Target.getInstructionsByEnumValue());
+ emitWebAssemblyDisassemblerTables(OS, Target.getInstructions());
return;
}
diff --git a/llvm/utils/TableGen/InstrDocsEmitter.cpp b/llvm/utils/TableGen/InstrDocsEmitter.cpp
index a8a234675dec1..7ca34ad05a72d 100644
--- a/llvm/utils/TableGen/InstrDocsEmitter.cpp
+++ b/llvm/utils/TableGen/InstrDocsEmitter.cpp
@@ -72,7 +72,7 @@ static void EmitInstrDocs(const RecordKeeper &RK, raw_ostream &OS) {
writeTitle(Title, OS);
OS << "\n";
- for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *II : Target.getInstructions()) {
const Record *Inst = II->TheDef;
// Don't print the target-independent instructions.
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index d5b6692652f9d..f028fcd082642 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -201,7 +201,7 @@ InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
OperandInfoMapTy &OperandInfoMap) {
const CodeGenTarget &Target = CDP.getTargetInfo();
unsigned Offset = 0;
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
OperandInfoTy OperandInfo = GetOperandInfo(*Inst);
if (OperandInfoMap.try_emplace(OperandInfo, Offset).second) {
OperandInfoList.push_back(OperandInfo);
@@ -645,7 +645,7 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
Target.getName(), "", "computeAvailableFeatures", SubtargetFeatures, OS);
std::vector<std::vector<const Record *>> FeatureBitsets;
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
FeatureBitsets.emplace_back();
for (const Record *Predicate :
Inst->TheDef->getValueAsListOfDefs("Predicates")) {
@@ -696,7 +696,7 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
<< " static constexpr " << getMinimalTypeForRange(FeatureBitsets.size())
<< " RequiredFeaturesRefs[] = {\n";
unsigned InstIdx = 0;
- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *Inst : Target.getInstructions()) {
OS << " CEFBS";
unsigned NumPredicates = 0;
for (const Record *Predicate :
@@ -818,7 +818,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
const CodeGenTarget &Target = CDP.getTargetInfo();
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
- Target.getInstructionsByEnumValue();
+ Target.getInstructions();
emitEnums(OS, NumberedInstructions);
@@ -1058,7 +1058,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
ArrayRef<const CodeGenInstruction *> TargetInstructions =
- Target.getTargetInstructionsByEnumValue();
+ Target.getTargetInstructions();
if (HasUseNamedOperandTable) {
Timer.startTimer("Emit operand name mappings");
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index bcc5712b9154c..d63570a88a4cb 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -625,7 +625,7 @@ void X86FoldTablesEmitter::run(raw_ostream &OS) {
std::map<uint8_t, std::vector<const CodeGenInstruction *>> RegInsts;
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
- Target.getInstructionsByEnumValue();
+ Target.getInstructions();
for (const CodeGenInstruction *Inst : NumberedInstructions) {
const Record *Rec = Inst->TheDef;
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 5a10aba8f357d..2e8351c951980 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -373,8 +373,7 @@ void X86InstrMappingEmitter::emitSSE2AVXTable(
void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitSourceFileHeader("X86 instruction mapping", OS);
- ArrayRef<const CodeGenInstruction *> Insts =
- Target.getInstructionsByEnumValue();
+ ArrayRef<const CodeGenInstruction *> Insts = Target.getInstructions();
printClassDef(OS);
emitCompressEVEXTable(Insts, OS);
emitNFTransformTable(Insts, OS);
diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp
index ddbfb2af9869f..f469fcabf7c3a 100644
--- a/llvm/utils/TableGen/X86MnemonicTables.cpp
+++ b/llvm/utils/TableGen/X86MnemonicTables.cpp
@@ -40,7 +40,7 @@ void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
// Hold all instructions grouped by mnemonic
StringMap<SmallVector<const CodeGenInstruction *, 0>> MnemonicToCGInstrMap;
- for (const CodeGenInstruction *I : Target.getInstructionsByEnumValue()) {
+ for (const CodeGenInstruction *I : Target.getInstructions()) {
const Record *Def = I->TheDef;
// Filter non-X86 instructions.
if (!Def->isSubClassOf("X86Inst"))
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