[llvm] [RISCV][VLOPT] Add support for vfmerge.vfm and vfmv.v.f (PR #146692)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 2 07:20:57 PDT 2025
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/146692
>From 35c518aaee21321e57425154028facb12704085d Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 2 Jul 2025 14:19:43 +0100
Subject: [PATCH 1/3] Precommit tests
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 42 ++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index 1cbb980aebffc..74807534a1294 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -4540,6 +4540,48 @@ define <vscale x 4 x float> @vfsgnjx_vf(<vscale x 4 x float> %a, float %b, iXLen
ret <vscale x 4 x float> %2
}
+define <vscale x 4 x float> @vfmerge_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x i1> %c, iXLen %vl) {
+; NOVLOPT-LABEL: vfmerge_vf:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; NOVLOPT-NEXT: vfmerge.vfm v10, v8, fa0, v0
+; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; NOVLOPT-NEXT: vfadd.vv v8, v10, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vfmerge_vf:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; VLOPT-NEXT: vfmerge.vfm v10, v8, fa0, v0
+; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; VLOPT-NEXT: vfadd.vv v8, v10, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 4 x float> @llvm.riscv.vfmerge(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, <vscale x 4 x i1> %c, iXLen -1)
+ %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)
+ ret <vscale x 4 x float> %2
+}
+
+define <vscale x 4 x float> @vfmv_v_f(<vscale x 4 x float> %a, float %b, iXLen %vl) {
+; NOVLOPT-LABEL: vfmv_v_f:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; NOVLOPT-NEXT: vfmv.v.f v10, fa0
+; NOVLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; NOVLOPT-NEXT: vfadd.vv v8, v10, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vfmv_v_f:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; VLOPT-NEXT: vfmv.v.f v10, fa0
+; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; VLOPT-NEXT: vfadd.vv v8, v10, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f(<vscale x 4 x float> poison, float %b, iXLen -1)
+ %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)
+ ret <vscale x 4 x float> %2
+}
+
define <vscale x 4 x float> @vfmacc_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {
; NOVLOPT-LABEL: vfmacc_vv:
; NOVLOPT: # %bb.0:
>From f59af75c83b4c12083d933343fc8cd93cc024558 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 2 Jul 2025 14:22:28 +0100
Subject: [PATCH 2/3] [RISCV][VLOPT] Add support for vfmerge.vfm and vfmv.v.f
I noticed these were missing when seeing some extra vl toggles with EVL tail folding.
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 4 ++++
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 6 ++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index d7aa85048eeda..9852b6b755144 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1119,6 +1119,10 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VMFLE_VV:
case RISCV::VMFGT_VF:
case RISCV::VMFGE_VF:
+ // Vector Floating-Point Merge Instruction
+ case RISCV::VFMERGE_VFM:
+ // Vector Floating-Point Move Instruction
+ case RISCV::VFMV_V_F:
// Single-Width Floating-Point/Integer Type-Convert Instructions
case RISCV::VFCVT_XU_F_V:
case RISCV::VFCVT_X_F_V:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index 74807534a1294..f4f194de644a0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -4551,9 +4551,8 @@ define <vscale x 4 x float> @vfmerge_vf(<vscale x 4 x float> %a, float %b, <vsca
;
; VLOPT-LABEL: vfmerge_vf:
; VLOPT: # %bb.0:
-; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; VLOPT-NEXT: vfmerge.vfm v10, v8, fa0, v0
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; VLOPT-NEXT: vfmerge.vfm v10, v8, fa0, v0
; VLOPT-NEXT: vfadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x float> @llvm.riscv.vfmerge(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, <vscale x 4 x i1> %c, iXLen -1)
@@ -4572,9 +4571,8 @@ define <vscale x 4 x float> @vfmv_v_f(<vscale x 4 x float> %a, float %b, iXLen %
;
; VLOPT-LABEL: vfmv_v_f:
; VLOPT: # %bb.0:
-; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; VLOPT-NEXT: vfmv.v.f v10, fa0
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; VLOPT-NEXT: vfmv.v.f v10, fa0
; VLOPT-NEXT: vfadd.vv v8, v10, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f(<vscale x 4 x float> poison, float %b, iXLen -1)
>From c96931be95b9ed1ab7567c5bc88ebb1f0d0450f0 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 2 Jul 2025 15:20:44 +0100
Subject: [PATCH 3/3] Update tests
---
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 96 +++++++------------
.../test/CodeGen/RISCV/rvv/vfma-vp-combine.ll | 6 +-
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 3 +-
3 files changed, 35 insertions(+), 70 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 9972df97ad9f4..8495dfe350729 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -299,9 +299,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.v.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vmfeq.vf v8, v8, fa5, v0.t
; CHECK-NEXT: vmfeq.vv v9, v9, v9, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -318,9 +317,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1bf16(<vscale x 1 x bfloat> %va, b
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.v.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vmfeq.vf v8, v8, fa5, v0.t
; CHECK-NEXT: vmfeq.vv v9, v9, v9, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -628,9 +626,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.v.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vmfne.vf v8, v8, fa5, v0.t
; CHECK-NEXT: vmfne.vv v9, v9, v9, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8
@@ -647,9 +644,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1bf16(<vscale x 1 x bfloat> %va, b
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.v.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vmfne.vf v8, v8, fa5, v0.t
; CHECK-NEXT: vmfne.vv v9, v9, v9, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9
@@ -978,9 +974,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat
; CHECK-LABEL: fcmp_ord_vf_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vmfeq.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -998,9 +993,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8bf16(<vscale x 8 x bfloat> %va, b
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vmfeq.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -1314,9 +1308,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat
; CHECK-LABEL: fcmp_uno_vf_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vmfne.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -1334,9 +1327,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8bf16(<vscale x 8 x bfloat> %va, b
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
; CHECK-NEXT: vmfne.vf v10, v12, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -1968,9 +1960,8 @@ define <vscale x 1 x i1> @fcmp_ord_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_ord_vf_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
; ZVFH-NEXT: vmand.mm v0, v8, v9
@@ -1981,9 +1972,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmv.v.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vf v8, v8, fa5, v0.t
; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t
; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
@@ -1997,9 +1987,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_ord_vf_swap_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
; ZVFH-NEXT: vmand.mm v0, v9, v8
@@ -2010,9 +1999,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmv.v.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vf v8, v8, fa5, v0.t
; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t
; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
@@ -2451,9 +2439,8 @@ define <vscale x 1 x i1> @fcmp_uno_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_uno_vf_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
; ZVFH-NEXT: vmor.mm v0, v8, v9
@@ -2464,9 +2451,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmv.v.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vf v8, v8, fa5, v0.t
; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t
; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
@@ -2480,9 +2466,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_uno_vf_swap_nxv1f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
; ZVFH-NEXT: vmor.mm v0, v9, v8
@@ -2493,9 +2478,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmv.v.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vf v8, v8, fa5, v0.t
; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t
; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
@@ -2966,9 +2950,8 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_ord_vf_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vmfeq.vf v12, v10, fa0, v0.t
; ZVFH-NEXT: vmfeq.vv v10, v8, v8, v0.t
; ZVFH-NEXT: vmand.mm v0, v10, v12
@@ -2977,9 +2960,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vmfeq.vf v10, v12, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -2996,9 +2978,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_ord_vf_swap_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vmfeq.vf v12, v10, fa0, v0.t
; ZVFH-NEXT: vmfeq.vv v10, v8, v8, v0.t
; ZVFH-NEXT: vmand.mm v0, v12, v10
@@ -3007,9 +2988,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vmfeq.vf v10, v12, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -3459,9 +3439,8 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_uno_vf_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vmfne.vf v12, v10, fa0, v0.t
; ZVFH-NEXT: vmfne.vv v10, v8, v8, v0.t
; ZVFH-NEXT: vmor.mm v0, v10, v12
@@ -3470,9 +3449,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vmfne.vf v10, v12, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -3489,9 +3467,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: fcmp_uno_vf_swap_nxv8f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
; ZVFH-NEXT: vmfne.vf v12, v10, fa0, v0.t
; ZVFH-NEXT: vmfne.vv v10, v8, v8, v0.t
; ZVFH-NEXT: vmor.mm v0, v12, v10
@@ -3500,9 +3477,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
; ZVFHMIN-NEXT: vmfne.vf v10, v12, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -4001,9 +3977,8 @@ define <vscale x 1 x i1> @fcmp_ord_vv_nxv1f64(<vscale x 1 x double> %va, <vscale
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -4017,9 +3992,8 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -4267,9 +4241,8 @@ define <vscale x 1 x i1> @fcmp_uno_vv_nxv1f64(<vscale x 1 x double> %va, <vscale
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9
@@ -4283,9 +4256,8 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8
@@ -4551,9 +4523,8 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v16, v24
@@ -4567,9 +4538,8 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v24, v16
@@ -4820,9 +4790,8 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v24
@@ -4836,9 +4805,8 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
index 35bed86d61176..03e6e6b7a624d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
@@ -30,9 +30,8 @@ define <vscale x 1 x double> @test2(<vscale x 1 x double> %a, <vscale x 1 x i1>
; CHECK-NEXT: fld fa5, %lo(.LCPI1_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI1_1)
; CHECK-NEXT: fld fa4, %lo(.LCPI1_1)(a1)
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa5
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
; CHECK-NEXT: vfadd.vf v9, v9, fa4, v0.t
; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -49,9 +48,8 @@ define <vscale x 1 x double> @test3(<vscale x 1 x double> %a, <vscale x 1 x doub
; CHECK-NEXT: fld fa5, %lo(.LCPI2_0)(a1)
; CHECK-NEXT: lui a1, %hi(.LCPI2_1)
; CHECK-NEXT: fld fa4, %lo(.LCPI2_1)(a1)
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa5
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa5
; CHECK-NEXT: vfmul.vf v10, v10, fa4, v0.t
; CHECK-NEXT: vfmadd.vv v10, v8, v9, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 8b48dc43eca29..f0e62cbc2d6ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -307,9 +307,8 @@ define <vscale x 1 x double> @test16(i64 %avl, double %a, <vscale x 1 x double>
; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64, mf2, ta, ma
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vfadd.vv v8, v9, v8
; CHECK-NEXT: ret
entry:
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