[llvm] [LLVM][AArch64] Relax SVE/SME codegen predicates. (PR #145322)

[Paul Walker via llvm-commits]

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@@ -269,32 +269,38 @@ def HasNonStreamingSVE_or_SSVE_BitPerm
                 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm),
                 "sve or ssve-bitperm">;
 def HasNonStreamingSVE_or_SSVE_FEXPA
-    : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
+    : Predicate<"Subtarget->isSVEAvailable() ||"
                 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
                 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_FEXPA),
                 "sve or ssve-fexpa">;
 
 def HasSVE2_or_SME
-    : Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
+    : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME())">,
                 AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
                 "sve2 or sme">;
-def HasSVE2_or_SME2
-    : Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
+def HasNonStreamingSVE2_or_SME2
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paulwalker-arm wrote:

I've tried to order the combined predicates based on the required SVE feature so that, for example, all SVE2 features are kept together.

https://github.com/llvm/llvm-project/pull/145322