[clang] [llvm] AMDGPU: Implement tensor load and store instructions for gfx1250 (PR #146636)
Tim Gymnich via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 2 03:23:08 PDT 2025
================
@@ -5354,6 +5368,22 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case Intrinsic::amdgcn_pops_exiting_wave_id:
return getDefaultMappingSOP(MI);
+ case Intrinsic::amdgcn_tensor_load_to_lds_d2:
+ case Intrinsic::amdgcn_tensor_store_from_lds_d2:
+ case Intrinsic::amdgcn_tensor_load_to_lds:
+ case Intrinsic::amdgcn_tensor_store_from_lds: {
+ // Lie and claim everything is legal, even all operands need to be
+ // SGPRs. applyMapping will have to deal with it with readfirstlane.
+ for (unsigned I = 1; I < MI.getNumOperands(); ++I) {
+ if (MI.getOperand(I).isReg()) {
+ Register Reg = MI.getOperand(I).getReg();
+ auto OpBank = getRegBankID(Reg, MRI);
+ unsigned Size = getSizeInBits(Reg, MRI, *TRI);
+ OpdsMapping[I] = AMDGPU::getValueMapping(OpBank, Size);
+ }
+ }
----------------
tgymnich wrote:
```suggestion
for (Register Reg : MI.all_uses()) {
auto OpBank = getRegBankID(Reg, MRI);
unsigned Size = getSizeInBits(Reg, MRI, *TRI);
OpdsMapping[I] = AMDGPU::getValueMapping(OpBank, Size);
}
```
https://github.com/llvm/llvm-project/pull/146636
More information about the llvm-commits
mailing list