[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)

[Lakshay Kumar via llvm-commits]

================
@@ -0,0 +1,82 @@
+# REQUIRES: aarch64-registered-target
+
+
+
+// Test for omitting OperandType::OPERAND_UNKNOWN
+
+// ADDXri: ADD Xd, Xn, #imm{, shift}
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_latency
+# ADDXri_latency-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
+# ADDXri_latency:      ---
+# ADDXri_latency-NEXT: mode: latency
+# ADDXri_latency-NEXT: key:
+# ADDXri_latency-NEXT:   instructions:
+# ADDXri_latency-NEXT:     ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
+# ADDXri_latency: ...
+
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_throughput
+# ADDXri_throughput-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
+# ADDXri_throughput:      ---
+# ADDXri_throughput-NEXT: mode: inverse_throughput
+# ADDXri_throughput-NEXT: key:
+# ADDXri_throughput-NEXT:   instructions:
+# ADDXri_throughput-NEXT:     ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
+# ADDXri_throughput: ...
+
+// MOVIv2s_msl: MOVI vd, #imm{, shift}
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency  --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput
+# MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
+
+// TODO: Update this test when serial execution strategy is added
+# MOVIv2s_msl_latency: MOVIv2s_msl: No strategy found to make the execution serial
+
+
+# MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
+# MOVIv2s_msl_throughput: ---
+# MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput
+# MOVIv2s_msl_throughput-NEXT: key: 
+# MOVIv2s_msl_throughput-NEXT:   instructions:
+# MOVIv2s_msl_throughput-NEXT:     MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x8
----------------
lakshayk-nv wrote:

Thanks, I looked into ISel Lowering and Instruction Selector for AArch64 and required imm value is 264 for `2s` variants and 272 for `4s`.
The previous value of 8, was added after observing assert of 8 or 16 for shift value in `AArch64MCCodeEmitter.cpp:getMoveVecShifterOpValue()`

```
$ build/bin/llvm-exegesis --debug-only="" -mcpu=neoverse-v2 -mode=inverse_throughput --opcode-name=MOVIv4s_msl --dump-object-to-disk=a.o
Check generated assembly with: /usr/bin/objdump -d a.o
---
mode:            inverse_throughput
key:
  instructions:
    - 'MOVIv4s_msl Q4 i_0x1 i_0x110'
  config:          ''
  register_initial_values: []
cpu_name:        neoverse-v2
llvm_triple:     aarch64-unknown-linux-gnu
min_instructions: 10000
measurements:
  - { key: inverse_throughput, value: 0.267, per_snippet_value: 0.267, validation_counters: {} }
error:           ''
info:            instruction is parallel, repeating a random one.
assembled_snippet: 24D4004F24D4004F24D4004F24D4004FC0035FD6
...

$  /usr/bin/objdump -d a.o
a.o:     file format elf64-littleaarch64
Disassembly of section .text:
0000000000000000 <foo>:
   0:   4f00d43a        movi    v26.4s, #0x1, msl #16.
   ...
  28:   d65f03c0        ret
```

https://github.com/llvm/llvm-project/pull/142529