[llvm] [InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (PR #146637)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 1 22:52:07 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/146637
This is alternative to #145965 that allows RegisterSDNode to be handled without making special case.
>From 127c547021f0b89364439056b9e97fd8cb069784 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 1 Jul 2025 22:35:06 -0700
Subject: [PATCH] [InstrEmitter] Use AddOperand in EmitCopyToRegClassNode.
This is alternative to #145965
---
.../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 9 ++---
llvm/test/CodeGen/AArch64/bf16_fast_math.ll | 36 +++++++++----------
.../CodeGen/AMDGPU/divergence-driven-ctpop.ll | 2 +-
.../fneg-fabs-divergence-driven-isel.ll | 6 ++--
llvm/test/CodeGen/ARM/fp16_fast_math.ll | 20 +++++------
.../aix32-vector-vararg-caller-split.ll | 8 ++---
llvm/test/CodeGen/PowerPC/nofpexcept.ll | 36 +++++++++----------
.../CodeGen/RISCV/rvv/vector-tuple-align.ll | 8 ++---
.../CodeGen/X86/apx/kmov-domain-assignment.ll | 8 ++---
llvm/test/CodeGen/X86/fp-intrinsics-flags.ll | 2 +-
llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 14 ++++----
llvm/test/CodeGen/X86/unpredictable-brcond.ll | 2 +-
.../vector-constrained-fp-intrinsics-flags.ll | 6 ++--
llvm/test/CodeGen/X86/x86-access-to-global.ll | 27 ++++++++++++++
14 files changed, 106 insertions(+), 78 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/x86-access-to-global.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 4b7a9127b3fc3..03d3e8eab35d0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -631,16 +631,17 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
void
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
VRBaseMapType &VRBaseMap) {
- Register VReg = getVR(Node->getOperand(0), VRBaseMap);
-
// Create the new VReg in the destination class and emit a copy.
unsigned DstRCIdx = Node->getConstantOperandVal(1);
const TargetRegisterClass *DstRC =
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
Register NewVReg = MRI->createVirtualRegister(DstRC);
- BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
- NewVReg).addReg(VReg);
+ const MCInstrDesc &II = TII->get(TargetOpcode::COPY);
+ MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
+ AddOperand(MIB, Node->getOperand(0), 1, &II, VRBaseMap, /*IsDebug=*/false,
+ /*IsClone=*/false, /*IsCloned*/ false);
+ MBB->insert(InsertPos, MIB);
SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
(void)isNew; // Silence compiler warning.
diff --git a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll
index 871ca12c9de77..e52c76fcc3f20 100644
--- a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll
+++ b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll
@@ -19,13 +19,13 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -65,13 +65,13 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -111,13 +111,13 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY4]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY4]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], killed [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr16 = COPY [[COPY5]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY6]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -161,13 +161,13 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -176,12 +176,12 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
+ ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
+ ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -232,13 +232,13 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z)
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -247,12 +247,12 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z)
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
+ ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
+ ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
@@ -299,13 +299,13 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]]
; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[FADDSrr]]
+ ; CHECK-NOBF16-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr]]
; CHECK-NOBF16-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY5]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri]], [[COPY5]]
; CHECK-NOBF16-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 32767
; CHECK-NOBF16-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]
+ ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]]
; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub
; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub
; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]]
@@ -314,12 +314,12 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) {
; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]]
; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub
; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr
- ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY [[FADDSrr1]]
+ ; CHECK-NOBF16-NEXT: [[COPY10:%[0-9]+]]:gpr32 = COPY killed [[FADDSrr1]]
; CHECK-NOBF16-NEXT: [[UBFMWri2:%[0-9]+]]:gpr32 = UBFMWri [[COPY10]], 16, 16
; CHECK-NOBF16-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr killed [[UBFMWri2]], [[COPY10]]
; CHECK-NOBF16-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr killed [[ADDWrr2]], [[MOVi32imm]]
; CHECK-NOBF16-NEXT: [[UBFMWri3:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr3]], 16, 31
- ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY [[UBFMWri3]]
+ ; CHECK-NOBF16-NEXT: [[COPY11:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri3]]
; CHECK-NOBF16-NEXT: [[COPY12:%[0-9]+]]:fpr16 = COPY [[COPY11]].hsub
; CHECK-NOBF16-NEXT: $h0 = COPY [[COPY12]]
; CHECK-NOBF16-NEXT: RET_ReallyLR implicit $h0
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
index 4a3a44d09210e..ea28af4508382 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
@@ -11,7 +11,7 @@ define amdgpu_kernel void @s_ctpop_i32(ptr addrspace(1) noalias %out, i32 %val)
; GCN-LABEL: name: s_ctpop_i64
; GCN: %[[BCNT:[0-9]+]]:sreg_32 = S_BCNT1_I32_B64
-; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY %[[BCNT]]
+; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY killed %[[BCNT]]
; GCN: %[[SREG2:[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: REG_SEQUENCE killed %[[SREG1]], %subreg.sub0, killed %[[SREG2]], %subreg.sub1
define amdgpu_kernel void @s_ctpop_i64(ptr addrspace(1) noalias %out, i64 %val) nounwind {
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
index d431503643d63..230b73a037221 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
@@ -398,7 +398,7 @@ define amdgpu_kernel void @uniform_fneg_f64(ptr addrspace(1) %out, ptr addrspace
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
; GCN: %[[XOR:[0-9]+]]:sreg_32 = S_XOR_B32 killed %[[HI32]], killed %[[SREG_MASK]]
-; GCN: %[[XOR_COPY:[0-9]+]]:sreg_32 = COPY %[[XOR]]
+; GCN: %[[XOR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[XOR]]
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[XOR_COPY]], %subreg.sub1
%in.gep = getelementptr inbounds double, ptr addrspace(1) %in, i64 %idx
@@ -440,7 +440,7 @@ define amdgpu_kernel void @uniform_fabs_f64(ptr addrspace(1) %out, ptr addrspace
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
; GCN: %[[AND:[0-9]+]]:sreg_32 = S_AND_B32 killed %[[HI32]], killed %[[SREG_MASK]]
-; GCN: %[[AND_COPY:[0-9]+]]:sreg_32 = COPY %[[AND]]
+; GCN: %[[AND_COPY:[0-9]+]]:sreg_32 = COPY killed %[[AND]]
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[AND_COPY]], %subreg.sub1
@@ -484,7 +484,7 @@ define amdgpu_kernel void @uniform_fneg_fabs_f64(ptr addrspace(1) %out, ptr addr
; GCN: %[[HI32:[0-9]+]]:sreg_32 = COPY %[[VREG64]].sub1
; GCN: %[[SREG_MASK:[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
; GCN: %[[OR:[0-9]+]]:sreg_32 = S_OR_B32 killed %[[HI32]], killed %[[SREG_MASK]]
-; GCN: %[[OR_COPY:[0-9]+]]:sreg_32 = COPY %[[OR]]
+; GCN: %[[OR_COPY:[0-9]+]]:sreg_32 = COPY killed %[[OR]]
; GCN: REG_SEQUENCE killed %[[LO32]], %subreg.sub0, killed %[[OR_COPY]], %subreg.sub1
diff --git a/llvm/test/CodeGen/ARM/fp16_fast_math.ll b/llvm/test/CodeGen/ARM/fp16_fast_math.ll
index 4c2e3ce4efcd5..165eb4b8af43e 100644
--- a/llvm/test/CodeGen/ARM/fp16_fast_math.ll
+++ b/llvm/test/CodeGen/ARM/fp16_fast_math.ll
@@ -21,7 +21,7 @@ define half @normal_fadd(half %x, half %y) {
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
@@ -55,7 +55,7 @@ define half @fast_fadd(half %x, half %y) {
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
@@ -89,7 +89,7 @@ define half @ninf_fadd(half %x, half %y) {
; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
@@ -129,13 +129,13 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) {
; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
- ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY [[COPY6]]
+ ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[VCVTBSH1]]
+ ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
@@ -177,7 +177,7 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) {
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY6]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
@@ -218,13 +218,13 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) {
; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[VCVTBSH]]
- ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY [[COPY6]]
+ ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]]
+ ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]]
; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg
; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg
- ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[VCVTBSH1]]
+ ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]]
; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]]
; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
;
diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
index 04f81124b6d8c..9e50455a0b42a 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
@@ -18,13 +18,13 @@ declare <4 x i32> @split_spill(double, double, double, ...)
; CHECK-DAG: [[ELEMENT1:%[0-9]+]]:gprc = LWZ 48, $r1 :: (load (s32))
; CHECK-DAG: [[ELEMENT2:%[0-9]+]]:gprc = LWZ 52, $r1 :: (load (s32))
; CHECK: [[FLOAT1SPLAT:%[0-9]+]]:vrrc = VSPLTISW 1
-; CHECK: [[FLOAT1COPY:%[0-9]+]]:vsrc = COPY [[FLOAT1SPLAT]]
+; CHECK: [[FLOAT1COPY:%[0-9]+]]:vsrc = COPY killed [[FLOAT1SPLAT]]
; CHECK: [[DOUBLE1:%[0-9]+]]:vsrc = XVCVSXWDP killed [[FLOAT1COPY]], implicit $rm
-; CHECK: [[DOUBLE1COPY:%[0-9]+]]:vsfrc = COPY [[DOUBLE1]]
+; CHECK: [[DOUBLE1COPY:%[0-9]+]]:vsfrc = COPY killed [[DOUBLE1]]
; CHECK: [[FLOAT2SPLAT:%[0-9]+]]:vrrc = VSPLTISW 2
-; CHECK: [[FLOAT2COPY:%[0-9]+]]:vsrc = COPY [[FLOAT2SPLAT]]
+; CHECK: [[FLOAT2COPY:%[0-9]+]]:vsrc = COPY killed [[FLOAT2SPLAT]]
; CHECK: [[DOUBLE2:%[0-9]+]]:vsrc = XVCVSXWDP killed [[FLOAT2COPY]], implicit $rm
-; CHECK: [[DOUBLE2COPY:%[0-9]+]]:vsfrc = COPY [[DOUBLE2]]
+; CHECK: [[DOUBLE2COPY:%[0-9]+]]:vsfrc = COPY killed [[DOUBLE2]]
; CHECK: [[DZERO:%[0-9]+]]:vsfrc = XXLXORdpz
; CHECK: [[DTOI1:%[0-9]+]]:gprc = LIS 16368
diff --git a/llvm/test/CodeGen/PowerPC/nofpexcept.ll b/llvm/test/CodeGen/PowerPC/nofpexcept.ll
index f764dfc2d2498..14c6e68fb9226 100644
--- a/llvm/test/CodeGen/PowerPC/nofpexcept.ll
+++ b/llvm/test/CodeGen/PowerPC/nofpexcept.ll
@@ -81,35 +81,35 @@ define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, ptr %addr1, ptr %addr2)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:f8rc = COPY $f2
; CHECK-NEXT: [[COPY4:%[0-9]+]]:f8rc = COPY $f1
; CHECK-NEXT: [[XSCVQPSWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSWZ [[COPY2]]
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vsfrc = COPY [[COPY5]].sub_64
- ; CHECK-NEXT: STIWX killed [[COPY6]], $zero8, [[COPY1]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY killed [[XSCVQPSWZ]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vsfrc = COPY killed [[COPY5]].sub_64
+ ; CHECK-NEXT: STIWX killed [[COPY6]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: [[XSCVQPUWZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUWZ [[COPY2]]
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vsfrc = COPY [[COPY7]].sub_64
- ; CHECK-NEXT: STIWX killed [[COPY8]], $zero8, [[COPY1]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY killed [[XSCVQPUWZ]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vsfrc = COPY killed [[COPY7]].sub_64
+ ; CHECK-NEXT: STIWX killed [[COPY8]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: [[XSCVQPSDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
; CHECK-NEXT: [[MFVRD:%[0-9]+]]:g8rc = nofpexcept MFVRD killed [[XSCVQPSDZ]]
; CHECK-NEXT: [[XSCVQPSDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
- ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vslrc = COPY [[XSCVQPSDZ1]]
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vfrc = COPY [[COPY9]].sub_64
- ; CHECK-NEXT: STXSD killed [[COPY10]], 0, [[COPY]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vslrc = COPY killed [[XSCVQPSDZ1]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vfrc = COPY killed [[COPY9]].sub_64
+ ; CHECK-NEXT: STXSD killed [[COPY10]], 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
; CHECK-NEXT: [[XSCVQPUDZ:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
; CHECK-NEXT: [[MFVRD1:%[0-9]+]]:g8rc = nofpexcept MFVRD killed [[XSCVQPUDZ]]
; CHECK-NEXT: [[XSCVQPUDZ1:%[0-9]+]]:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vslrc = COPY [[XSCVQPUDZ1]]
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vfrc = COPY [[COPY11]].sub_64
- ; CHECK-NEXT: STXSD killed [[COPY12]], 0, [[COPY]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vslrc = COPY killed [[XSCVQPUDZ1]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vfrc = COPY killed [[COPY11]].sub_64
+ ; CHECK-NEXT: STXSD killed [[COPY12]], 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
; CHECK-NEXT: [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm
; CHECK-NEXT: [[FADD:%[0-9]+]]:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
; CHECK-NEXT: MTFSFb 1, [[MFFS]], implicit-def $rm
; CHECK-NEXT: [[XSCVDPSXWS:%[0-9]+]]:vsfrc = nofpexcept XSCVDPSXWS killed [[FADD]], implicit $rm
- ; CHECK-NEXT: STIWX killed [[XSCVDPSXWS]], $zero8, [[COPY1]]
+ ; CHECK-NEXT: STIWX killed [[XSCVDPSXWS]], $zero8, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
; CHECK-NEXT: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
; CHECK-NEXT: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:f8rc = COPY killed [[DFLOADf32_]]
; CHECK-NEXT: [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY13]]
; CHECK-NEXT: [[COPY14:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
; CHECK-NEXT: [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
@@ -174,8 +174,8 @@ define signext i32 @q_to_i32(fp128 %m) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
; CHECK-NEXT: [[XSCVQPSWZ:%[0-9]+]]:vrrc = XSCVQPSWZ [[COPY]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY killed [[XSCVQPSWZ]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY killed [[COPY1]].sub_64
; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY2]]
; CHECK-NEXT: [[EXTSW_32_64_:%[0-9]+]]:g8rc = EXTSW_32_64 killed [[MFVSRWZ]]
; CHECK-NEXT: $x3 = COPY [[EXTSW_32_64_]]
@@ -222,8 +222,8 @@ define zeroext i32 @q_to_u32(fp128 %m) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
; CHECK-NEXT: [[XSCVQPUWZ:%[0-9]+]]:vrrc = XSCVQPUWZ [[COPY]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY killed [[XSCVQPUWZ]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY killed [[COPY1]].sub_64
; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY2]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[MFVSRWZ]], %subreg.sub_32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll b/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
index 4a24e2342fabc..3a461c8721440 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll
@@ -11,7 +11,7 @@ define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv8i8(pt
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoVLSEG2E8_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E8_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E8_V_M1_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E8_V_M1_]]
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
; CHECK-NEXT: PseudoRET implicit $v8_v9
entry:
@@ -27,7 +27,7 @@ define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv4i16(p
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoVLSEG2E16_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E16_V_M1 $noreg, [[COPY1]], [[COPY]], 4 /* e16 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 2)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E16_V_M1_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E16_V_M1_]]
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
; CHECK-NEXT: PseudoRET implicit $v8_v9
entry:
@@ -43,7 +43,7 @@ define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv2i32(p
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoVLSEG2E32_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E32_V_M1 $noreg, [[COPY1]], [[COPY]], 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 4)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E32_V_M1_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E32_V_M1_]]
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
; CHECK-NEXT: PseudoRET implicit $v8_v9
entry:
@@ -59,7 +59,7 @@ define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv1i64(p
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoVLSEG2E64_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E64_V_M1 $noreg, [[COPY1]], [[COPY]], 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 8)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E64_V_M1_]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E64_V_M1_]]
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
; CHECK-NEXT: PseudoRET implicit $v8_v9
entry:
diff --git a/llvm/test/CodeGen/X86/apx/kmov-domain-assignment.ll b/llvm/test/CodeGen/X86/apx/kmov-domain-assignment.ll
index e70e5ff80d959..a7fe8983f2f29 100644
--- a/llvm/test/CodeGen/X86/apx/kmov-domain-assignment.ll
+++ b/llvm/test/CodeGen/X86/apx/kmov-domain-assignment.ll
@@ -22,8 +22,8 @@ define void @test_fcmp_storei1(i1 %cond, ptr %fptr, ptr %iptr, float %f1, float
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[VCMPSSZrri:%[0-9]+]]:vk1 = nofpexcept VCMPSSZrri [[COPY3]], [[COPY2]], 0, implicit $mxcsr
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vk16 = COPY [[VCMPSSZrri]]
- ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vk32 = COPY [[COPY7]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vk16 = COPY killed [[VCMPSSZrri]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vk32 = COPY killed [[COPY7]]
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vk8 = COPY [[COPY8]]
; CHECK-NEXT: JMP_1 %bb.3
; CHECK-NEXT: {{ $}}
@@ -31,8 +31,8 @@ define void @test_fcmp_storei1(i1 %cond, ptr %fptr, ptr %iptr, float %f1, float
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[VCMPSSZrri1:%[0-9]+]]:vk1 = nofpexcept VCMPSSZrri [[COPY1]], [[COPY]], 0, implicit $mxcsr
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vk16 = COPY [[VCMPSSZrri1]]
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vk32 = COPY [[COPY10]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vk16 = COPY killed [[VCMPSSZrri1]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vk32 = COPY killed [[COPY10]]
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vk8 = COPY [[COPY11]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.exit:
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
index 4e36d5a31c3d9..bd32430fcedbd 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
@@ -60,7 +60,7 @@ define i8 @f20s8(double %x) #0 {
entry:
; CHECK-LABEL: name: f20s8
; CHECK: [[CVTTSD2SIrm:%[0-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load (s64) from %fixed-stack.0, align 16)
-; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY [[CVTTSD2SIrm]]
+; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY killed [[CVTTSD2SIrm]]
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: $al = COPY [[COPY1]]
; CHECK: RET 0, $al
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
index 78df4f685f6e9..42617c1573be5 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -35,15 +35,15 @@ define float @sqrt_ieee_ninf(float %f) #0 {
; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[VMULSSrr5]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY]]
; CHECK-NEXT: [[VPBROADCASTDrm:%[0-9]+]]:vr128 = VPBROADCASTDrm $rip, 1, $noreg, %const.2, $noreg :: (load (s32) from constant-pool)
; CHECK-NEXT: [[VPANDrr:%[0-9]+]]:vr128 = VPANDrr killed [[COPY2]], killed [[VPBROADCASTDrm]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fr32 = COPY [[VPANDrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fr32 = COPY killed [[VPANDrr]]
; CHECK-NEXT: [[VCMPSSrmi:%[0-9]+]]:fr32 = nofpexcept VCMPSSrmi killed [[COPY3]], $rip, 1, $noreg, %const.3, $noreg, 1, implicit $mxcsr :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vr128 = COPY [[VCMPSSrmi]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vr128 = COPY killed [[VCMPSSrmi]]
; CHECK-NEXT: [[VPANDNrr:%[0-9]+]]:vr128 = VPANDNrr killed [[COPY4]], killed [[COPY1]]
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fr32 = COPY [[VPANDNrr]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fr32 = COPY killed [[VPANDNrr]]
; CHECK-NEXT: $xmm0 = COPY [[COPY5]]
; CHECK-NEXT: RET 0, $xmm0
%call = tail call ninf afn float @llvm.sqrt.f32(float %f)
@@ -82,12 +82,12 @@ define float @sqrt_daz_ninf(float %f) #1 {
; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[VMULSSrr5]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
; CHECK-NEXT: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
; CHECK-NEXT: [[VCMPSSrri:%[0-9]+]]:fr32 = nofpexcept VCMPSSrri [[COPY]], killed [[FsFLD0SS]], 0, implicit $mxcsr
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY [[VCMPSSrri]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY killed [[VCMPSSrri]]
; CHECK-NEXT: [[VPANDNrr:%[0-9]+]]:vr128 = VPANDNrr killed [[COPY2]], killed [[COPY1]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fr32 = COPY [[VPANDNrr]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fr32 = COPY killed [[VPANDNrr]]
; CHECK-NEXT: $xmm0 = COPY [[COPY3]]
; CHECK-NEXT: RET 0, $xmm0
%call = tail call ninf afn float @llvm.sqrt.f32(float %f)
diff --git a/llvm/test/CodeGen/X86/unpredictable-brcond.ll b/llvm/test/CodeGen/X86/unpredictable-brcond.ll
index 12411f1c49f2d..bb44171d20d65 100644
--- a/llvm/test/CodeGen/X86/unpredictable-brcond.ll
+++ b/llvm/test/CodeGen/X86/unpredictable-brcond.ll
@@ -87,7 +87,7 @@ define void @isint_branch(double %d) nounwind {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[COPY]]
; CHECK-NEXT: [[CVTTPD2DQrr:%[0-9]+]]:vr128 = nofpexcept CVTTPD2DQrr killed [[COPY1]], implicit $mxcsr
; CHECK-NEXT: [[CVTDQ2PDrr:%[0-9]+]]:vr128 = CVTDQ2PDrr killed [[CVTTPD2DQrr]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[CVTDQ2PDrr]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY killed [[CVTDQ2PDrr]]
; CHECK-NEXT: nofpexcept UCOMISDrr [[COPY]], killed [[COPY2]], implicit-def $eflags, implicit $mxcsr
; CHECK-NEXT: unpredictable JCC_1 %bb.2, 5, implicit $eflags
; CHECK-NEXT: unpredictable JCC_1 %bb.2, 10, implicit $eflags
diff --git a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
index 9c80720ae921a..d77934adf4cd1 100644
--- a/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
+++ b/llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll
@@ -18,10 +18,10 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 {
; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
; CHECK: [[ADDSSrm:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load (s32) from constant-pool)
; CHECK: [[ADDSSrm1:%[0-9]+]]:fr32 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load (s32) from constant-pool)
-; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY [[ADDSSrm1]]
-; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[ADDSSrm]]
+; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY killed [[ADDSSrm1]]
+; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[ADDSSrm]]
; CHECK: [[UNPCKLPSrr:%[0-9]+]]:vr128 = UNPCKLPSrr [[COPY1]], killed [[COPY]]
-; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY [[ADDSSrr]]
+; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY killed [[ADDSSrr]]
; CHECK: [[UNPCKLPDrr:%[0-9]+]]:vr128 = UNPCKLPDrr [[UNPCKLPSrr]], killed [[COPY2]]
; CHECK: $xmm0 = COPY [[UNPCKLPDrr]]
; CHECK: RET 0, $xmm0
diff --git a/llvm/test/CodeGen/X86/x86-access-to-global.ll b/llvm/test/CodeGen/X86/x86-access-to-global.ll
new file mode 100644
index 0000000000000..9e09a035ac519
--- /dev/null
+++ b/llvm/test/CodeGen/X86/x86-access-to-global.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -relocation-model=pic < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+ at .str = external dso_local global i32
+
+define i1 @test() {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: calll .L0$pb
+; CHECK-NEXT: .cfi_adjust_cfa_offset 4
+; CHECK-NEXT: .L0$pb:
+; CHECK-NEXT: popl %eax
+; CHECK-NEXT: .cfi_adjust_cfa_offset -4
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
+; CHECK-NEXT: movl $.str at GOTOFF, %ecx
+; CHECK-NEXT: addb %al, %cl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retl
+ %i = ptrtoint ptr @.str to i8
+ %p = zext i8 %i to i32
+ %c = icmp eq i32 %p, 0
+ ret i1 %c
+}
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