[llvm] [AMDGPU] Ensure non-reserved CSR spilled regs are live-in (PR #146427)

[Matt Arsenault via llvm-commits]

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@@ -995,6 +996,12 @@ void SIFrameLowering::emitCSRSpillStores(
         }
       };
 
+  for (const Register &Reg : make_first_range(WWMScratchRegs)) {
+    if (!MRI.isReserved(Reg)) {
+      MRI.addLiveIn(Reg);
+      MBB.addLiveIn(Reg);
+    }
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arsenm wrote:

I thought all WWM registers should be reserved at this point, this is papering over not adding them to reserved? 

https://github.com/llvm/llvm-project/pull/146427