[llvm] [AArch64][Codegen]Transform saturating smull to sqdmulh (PR #143671)

[Nashe Mncube via llvm-commits]

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@@ -20918,6 +20928,79 @@ static SDValue performBuildVectorCombine(SDNode *N,
   return SDValue();
 }
 
+// A special combine for the sqdmulh family of instructions.
+// smin( sra ( mul( sext v0, sext v1 ) ), SHIFT_AMOUNT ),
+// SATURATING_VAL ) can be reduced to sext(sqdmulh(...))
+static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
+
+  if (N->getOpcode() != ISD::TRUNCATE)
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nasherm wrote:

Ahhh, looking into this a bit more, I'm finding that performDAGCombine isn't matching on SMINs for some other reason than visibility. Even if the SMIN is a parent node the performDAGCombine step isn't matching with that node for some reason. So I think my assumption about how 'performDAGCombine' traverses the DAG is incorrect. Investigating

https://github.com/llvm/llvm-project/pull/143671