[llvm] [ARM] Copy (SELECT_CC setgt, iN lhs, -1, 1, -1) -> (OR (ASR lhs, N-1), 1 from AArch64 to ARM (PR #146561)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

<details>
<summary>Changes</summary>

It works perfectly for ARM too.

---
Full diff: https://github.com/llvm/llvm-project/pull/146561.diff


2 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+15) 
- (added) llvm/test/CodeGen/ARM/cmp-select-sign.ll (+136) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2f89e23993385..735184115e3b8 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5510,6 +5510,21 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
   SDValue FalseVal = Op.getOperand(3);
   ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
   ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
+  ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
+  if (LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
+    // Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
+    // into (OR (ASR lhs, N-1), 1), which requires less instructions for the
+    // supported types.
+    if (CC == ISD::SETGT && RHSC && RHSC->isAllOnes() && CTVal && CFVal &&
+        CTVal->isOne() && CFVal->isAllOnes() &&
+        LHS.getValueType() == TrueVal.getValueType()) {
+      EVT VT = LHS.getValueType();
+      SDValue Shift =
+          DAG.getNode(ISD::SRA, dl, VT, LHS,
+                      DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
+      return DAG.getNode(ISD::OR, dl, VT, Shift, DAG.getConstant(1, dl, VT));
+    }
+  }
 
   if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
       LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
diff --git a/llvm/test/CodeGen/ARM/cmp-select-sign.ll b/llvm/test/CodeGen/ARM/cmp-select-sign.ll
new file mode 100644
index 0000000000000..34f342e2f207e
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cmp-select-sign.ll
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a < %s | FileCheck %s --check-prefix=ARM
+; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB
+; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2
+
+define i3 @sign_i3(i3 %a) {
+; ARM-LABEL: sign_i3:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsl r0, r0, #29
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    orr r0, r1, r0, asr #31
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: sign_i3:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r0, #29
+; THUMB-NEXT:    asrs r1, r0, #31
+; THUMB-NEXT:    movs r0, #1
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: sign_i3:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r0, #29
+; THUMB2-NEXT:    movs r1, #1
+; THUMB2-NEXT:    orr.w r0, r1, r0, asr #31
+; THUMB2-NEXT:    bx lr
+  %c = icmp sgt i3 %a, -1
+  %res = select i1 %c, i3 1, i3 -1
+  ret i3 %res
+}
+
+define i4 @sign_i4(i4 %a) {
+; ARM-LABEL: sign_i4:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsl r0, r0, #28
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    orr r0, r1, r0, asr #31
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: sign_i4:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r0, #28
+; THUMB-NEXT:    asrs r1, r0, #31
+; THUMB-NEXT:    movs r0, #1
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: sign_i4:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r0, #28
+; THUMB2-NEXT:    movs r1, #1
+; THUMB2-NEXT:    orr.w r0, r1, r0, asr #31
+; THUMB2-NEXT:    bx lr
+  %c = icmp sgt i4 %a, -1
+  %res = select i1 %c, i4 1, i4 -1
+  ret i4 %res
+}
+
+define i8 @sign_i8(i8 %a) {
+; ARM-LABEL: sign_i8:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsl r0, r0, #24
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    orr r0, r1, r0, asr #31
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: sign_i8:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r0, #24
+; THUMB-NEXT:    asrs r1, r0, #31
+; THUMB-NEXT:    movs r0, #1
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: sign_i8:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r0, #24
+; THUMB2-NEXT:    movs r1, #1
+; THUMB2-NEXT:    orr.w r0, r1, r0, asr #31
+; THUMB2-NEXT:    bx lr
+  %c = icmp sgt i8 %a, -1
+  %res = select i1 %c, i8 1, i8 -1
+  ret i8 %res
+}
+
+define i16 @sign_i16(i16 %a) {
+; ARM-LABEL: sign_i16:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsl r0, r0, #16
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    orr r0, r1, r0, asr #31
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: sign_i16:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r0, #16
+; THUMB-NEXT:    asrs r1, r0, #31
+; THUMB-NEXT:    movs r0, #1
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: sign_i16:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r0, #16
+; THUMB2-NEXT:    movs r1, #1
+; THUMB2-NEXT:    orr.w r0, r1, r0, asr #31
+; THUMB2-NEXT:    bx lr
+  %c = icmp sgt i16 %a, -1
+  %res = select i1 %c, i16 1, i16 -1
+  ret i16 %res
+}
+
+define i32 @sign_i32(i32 %a) {
+; ARM-LABEL: sign_i32:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    orr r0, r1, r0, asr #31
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: sign_i32:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    asrs r1, r0, #31
+; THUMB-NEXT:    movs r0, #1
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: sign_i32:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    movs r1, #1
+; THUMB2-NEXT:    orr.w r0, r1, r0, asr #31
+; THUMB2-NEXT:    bx lr
+  %c = icmp sgt i32 %a, -1
+  %res = select i1 %c, i32 1, i32 -1
+  ret i32 %res
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/146561