[llvm] [RISCV] Fix crash when trying to remove segment (PR #146524)

via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 1 08:53:01 PDT 2025


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@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @strlen16_vec(ptr %s) {
+; CHECK-LABEL: strlen16_vec:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li a1, 0
+; CHECK-NEXT:    li a2, 16
+; CHECK-NEXT:    li a3, -1
+; CHECK-NEXT:    li a4, 16
+; CHECK-NEXT:    j .LBB0_2
+; CHECK-NEXT:  .LBB0_1: # %while.body
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    add a1, a6, a1
+; CHECK-NEXT:    bne a5, a3, .LBB0_5
+; CHECK-NEXT:  .LBB0_2: # %while.cond
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    bne a4, a2, .LBB0_5
+; CHECK-NEXT:  # %bb.3: # %while.body
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
+; CHECK-NEXT:    vle16ff.v v8, (a0)
+; CHECK-NEXT:    csrr a4, vl
+; CHECK-NEXT:    vmseq.vi v8, v8, 0
+; CHECK-NEXT:    vfirst.m a5, v8
+; CHECK-NEXT:    mv a6, a4
+; CHECK-NEXT:    beq a5, a3, .LBB0_1
+; CHECK-NEXT:  # %bb.4: # %while.body
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    mv a6, a5
+; CHECK-NEXT:    j .LBB0_1
+; CHECK-NEXT:  .LBB0_5: # %while.end
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:    ret
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.body, %entry
+  %new_vl.0 = phi i64 [ 16, %entry ], [ %2, %while.body ]
+  %len.0 = phi i64 [ 0, %entry ], [ %len.1, %while.body ]
+  %cmp = icmp eq i64 %new_vl.0, 16
+  br i1 %cmp, label %while.body, label %while.end
+
+while.body:                                       ; preds = %while.cond
+  %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> poison, ptr %s, i64 16)
+  %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 0
+  %2 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1
+  %3 = tail call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> %1, i16 0, i64 %2)
+  %4 = tail call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %3, i64 %2)
+  %cmp1 = icmp eq i64 %4, -1
+  %.13 = select i1 %cmp1, i64 %2, i64 %4
+  %len.1 = add i64 %.13, %len.0
+  br i1 %cmp1, label %while.cond, label %while.end
+
----------------
sc-clulzze wrote:

I reduced the test a bit, but could not get rid of while.cond block

https://github.com/llvm/llvm-project/pull/146524


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