[llvm] fd46e40 - [X86] detectZextAbsDiff - use m_SpecificVectorElementVT matcher. NFC. (#146498)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2025-07-01T11:59:37+01:00
New Revision: fd46e409a91f66764b3c9d19dd3d6d3eb48c61ff

URL: https://github.com/llvm/llvm-project/commit/fd46e409a91f66764b3c9d19dd3d6d3eb48c61ff
DIFF: https://github.com/llvm/llvm-project/commit/fd46e409a91f66764b3c9d19dd3d6d3eb48c61ff.diff

LOG: [X86] detectZextAbsDiff - use m_SpecificVectorElementVT matcher. NFC. (#146498)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 01f309ddd721c..232d055223f64 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45998,12 +45998,11 @@ static bool detectZextAbsDiff(SDValue Abs, SDValue &Op0, SDValue &Op1) {
   using namespace SDPatternMatch;
 
   // Check if the operands of the sub are zero-extended from vectors of i8.
-  EVT SrcVT0, SrcVT1;
-  return sd_match(Abs,
-                  m_Abs(m_Sub(m_AllOf(m_Value(Op0), m_ZExt(m_VT(SrcVT0))),
-                              m_AllOf(m_Value(Op1), m_ZExt(m_VT(SrcVT1)))))) &&
-         SrcVT0.getVectorElementType() == MVT::i8 &&
-         SrcVT1.getVectorElementType() == MVT::i8;
+  return sd_match(
+      Abs,
+      m_Abs(m_Sub(
+          m_AllOf(m_Value(Op0), m_ZExt(m_SpecificVectorElementVT(MVT::i8))),
+          m_AllOf(m_Value(Op1), m_ZExt(m_SpecificVectorElementVT(MVT::i8))))));
 }
 
 static SDValue createVPDPBUSD(SelectionDAG &DAG, SDValue LHS, SDValue RHS,