[llvm] 67b740b - [X86] Add diagnostic for fp128 inline assemble for 32-bit (#146458)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 30 21:39:47 PDT 2025
Author: Phoebe Wang
Date: 2025-07-01T12:39:43+08:00
New Revision: 67b740bd73a6ae1de8488a51929bb44f3b8ed30e
URL: https://github.com/llvm/llvm-project/commit/67b740bd73a6ae1de8488a51929bb44f3b8ed30e
DIFF: https://github.com/llvm/llvm-project/commit/67b740bd73a6ae1de8488a51929bb44f3b8ed30e.diff
LOG: [X86] Add diagnostic for fp128 inline assemble for 32-bit (#146458)
Suggested by Craig from #146259
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/pr43157.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 36920de8cb7c5..01f309ddd721c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61737,6 +61737,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::VR128XRegClass);
return std::make_pair(0U, &X86::VR128RegClass);
case MVT::f128:
+ if (!Subtarget.is64Bit())
+ break;
+ [[fallthrough]];
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
diff --git a/llvm/test/CodeGen/X86/pr43157.ll b/llvm/test/CodeGen/X86/pr43157.ll
index 2b333782f43a0..308a8b91d859e 100644
--- a/llvm/test/CodeGen/X86/pr43157.ll
+++ b/llvm/test/CodeGen/X86/pr43157.ll
@@ -1,6 +1,7 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc < %s -mtriple=i686-pc-linux -o - -mattr=+sse2 2>&1 | FileCheck %s --check-prefix=ERR
; RUN: llc < %s -mtriple=x86_64-pc-linux -o - -mattr=+mmx | FileCheck %s
+; ERR: error: couldn't allocate input reg for constraint 'x'
define void @foo(fp128 %x) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
More information about the llvm-commits
mailing list