[llvm] [VectorCombine] New folding pattern for extract/binop/shuffle chains (PR #145232)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

> @RKSimon Do you know where this pattern is generated from? If it is only introduced by SLP/LoopVec, can we just emit a reduction instead? Is this pattern left as is since the reduction is not supported by the target?

Its a standard SIMD pattern for C/C++ SSE/AVX code for reductions where the builtin isn't available - although it can get more complicated if wider vector types get split down the chain (1 x 512-bit -> 2 x 256-bit, 1 x 256-bit -> 2 x 128-bit etc.). Until recently the AVX512 _mm512_reduce_ intrinsics were implemented with a similar pattern, but they now mostly use the builtins.

https://github.com/llvm/llvm-project/pull/145232