[llvm] [AVR] Add LDS/STS disassemble (PR #146325)
Tom Vijlbrief via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 30 02:50:04 PDT 2025
https://github.com/tomtor created https://github.com/llvm/llvm-project/pull/146325
LDS/STS instructions are shown as `<unknown>` with `llvm-objdump -d`.
This PR adds the missing decode.
>From 0456f6f4af3af136ec476af61a1192429db42b62 Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief at gmail.com>
Date: Mon, 30 Jun 2025 10:05:25 +0200
Subject: [PATCH] Add LDS/STS disassemble
---
.../AVR/Disassembler/AVRDisassembler.cpp | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index c7a584868f4e6..d18bdf87ebf17 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -433,6 +433,22 @@ static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
+static DecodeStatus decodeLoadStore32(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ // Get the register that will be loaded or stored.
+ unsigned RegVal = GPRDecoderTable[(Insn >> 20) & 0x1f];
+
+ // Decode LDS/STS
+ if ((Insn & 0xfc0f0000) == 0x90000000) {
+ Inst.setOpcode((Insn & 0x02000000) ? AVR::STSKRr : AVR::LDSRdK);
+ Inst.addOperand(MCOperand::createReg(RegVal));
+ Inst.addOperand(MCOperand::createImm(Insn & 0xFFFF));
+ return MCDisassembler::Success;
+ }
+ return MCDisassembler::Fail;
+}
+
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn) {
if (Bytes.size() < 2) {
@@ -523,6 +539,10 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
return Result;
}
+ Result = decodeLoadStore32(Instr, Insn, Address, this);
+ if (Result != MCDisassembler::Fail)
+ return Result;
+
return MCDisassembler::Fail;
}
}
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