[clang] [llvm] [clang][AArch64] Parse more features in getHostCPUFeatures (PR #146323)

[Elvina Yakubova via llvm-commits]

https://github.com/ElvinaYakubova created https://github.com/llvm/llvm-project/pull/146323

None

>From e65f50b8c1e549a693d5e1f1dd597ed5bca40ffd Mon Sep 17 00:00:00 2001
From: Elvina Yakubova <eyakubova at nvidia.com>
Date: Thu, 26 Jun 2025 09:07:23 -0700
Subject: [PATCH] [clang][AArch64] Parse more features in getHostCPUFeatures

---
 clang/test/Driver/Inputs/cpunative/grace                  | 8 ++++++++
 clang/test/Driver/Inputs/cpunative/neoverse-v2            | 2 +-
 .../test/Driver/print-enabled-extensions/aarch64-grace.c  | 2 ++
 llvm/lib/TargetParser/Host.cpp                            | 5 +++++
 4 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/Driver/Inputs/cpunative/grace

diff --git a/clang/test/Driver/Inputs/cpunative/grace b/clang/test/Driver/Inputs/cpunative/grace
new file mode 100644
index 0000000000000..c3c8433415d7a
--- /dev/null
+++ b/clang/test/Driver/Inputs/cpunative/grace
@@ -0,0 +1,8 @@
+processor       : 0
+BogoMIPS        : 2000.00
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant     : 0x0
+CPU part        : 0xd4f
+CPU revision    : 0
diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-v2 b/clang/test/Driver/Inputs/cpunative/neoverse-v2
index c3c8433415d7a..e5494c33de0df 100644
--- a/clang/test/Driver/Inputs/cpunative/neoverse-v2
+++ b/clang/test/Driver/Inputs/cpunative/neoverse-v2
@@ -1,6 +1,6 @@
 processor       : 0
 BogoMIPS        : 2000.00
-Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop asimddp sve asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp sve2 svepmull svebitperm flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti
 CPU implementer : 0x41
 CPU architecture: 8
 CPU variant     : 0x0
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
index bb24dfbbc0702..dab8cdd7b3817 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -1,5 +1,7 @@
 // REQUIRES: aarch64-registered-target
 // RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+// RUN: export LLVM_CPUINFO=%S/../Inputs/cpunative/grace
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
 
 // CHECK: Extensions enabled for the given AArch64 target
 // CHECK-EMPTY:
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 5957e1befe2da..7791e36210451 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -2082,8 +2082,13 @@ const StringMap<bool> sys::getHostCPUFeatures() {
                                    .Case("fp", "fp-armv8")
                                    .Case("crc32", "crc")
                                    .Case("atomics", "lse")
+                                   .Case("sha3", "sha3")
+                                   .Case("sm4", "sm4")
                                    .Case("sve", "sve")
                                    .Case("sve2", "sve2")
+                                   .Case("sveaes", "sve-aes")
+                                   .Case("svesha3", "sve-sha3")
+                                   .Case("svesm4", "sve2-sm4")
 #else
                                    .Case("half", "fp16")
                                    .Case("neon", "neon")