[llvm] [AArch64][Codegen]Transform saturating smull to sqdmulh (PR #143671)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 29 13:24:28 PDT 2025
================
@@ -20717,6 +20717,83 @@ static SDValue performBuildVectorCombine(SDNode *N,
return SDValue();
}
+// A special combine for the vqdmulh family of instructions.
+// smin( sra ( mul( sext v0, sext v1 ) ), SHIFT_AMOUNT ),
+// SATURATING_VAL ) can be reduced to sext(sqdmulh(...))
+static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
+
+ if (N->getOpcode() != ISD::TRUNCATE)
+ return SDValue();
+
+ EVT VT = N->getValueType(0);
+
+ if (!VT.isVector() || VT.getScalarSizeInBits() > 64)
+ return SDValue();
+
+ SDValue SMin = N->getOperand(0);
+
+ if (SMin.getOpcode() != ISD::SMIN)
+ return SDValue();
+
+ ConstantSDNode *Clamp = isConstOrConstSplat(SMin.getOperand(1));
+
+ if (!Clamp)
+ return SDValue();
+
+ MVT ScalarType;
+ unsigned ShiftAmt = 0;
+ switch (Clamp->getSExtValue()) {
+ case (1ULL << 15) - 1:
+ ScalarType = MVT::i16;
+ ShiftAmt = 16;
+ break;
+ case (1ULL << 31) - 1:
+ ScalarType = MVT::i32;
+ ShiftAmt = 32;
+ break;
+ default:
+ return SDValue();
+ }
+
+ SDValue Sra = SMin.getOperand(0);
+ if (Sra.getOpcode() != ISD::SRA)
+ return SDValue();
+
+ ConstantSDNode *RightShiftVec = isConstOrConstSplat(Sra.getOperand(1));
+ if (!RightShiftVec)
+ return SDValue();
+ unsigned SExtValue = RightShiftVec->getSExtValue();
+
+ if (SExtValue != (ShiftAmt - 1))
+ return SDValue();
+
+ SDValue Mul = Sra.getOperand(0);
+ if (Mul.getOpcode() != ISD::MUL)
+ return SDValue();
+
+ SDValue SExt0 = Mul.getOperand(0);
+ SDValue SExt1 = Mul.getOperand(1);
+
+ if (SExt0.getOpcode() != ISD::SIGN_EXTEND ||
+ SExt1.getOpcode() != ISD::SIGN_EXTEND ||
+ SExt0.getValueType() != SExt1.getValueType())
----------------
davemgreen wrote:
SExt0.getOperand(0).getValueType() != SExt1.getOperand(0).getValueType())
https://github.com/llvm/llvm-project/pull/143671
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