[llvm] [NVPTX] support packed f32 instructions for sm_100+ (PR #126337)

[Princeton Ferro via llvm-commits]

================
@@ -5098,7 +5148,7 @@ static SDValue combinePackingMovIntoStore(SDNode *N,
   // Get the type of the operands being stored.
   EVT ElementVT = N->getOperand(Front).getValueType();
 
-  if (!Isv2x16VT(ElementVT))
+  if (!isPackedVectorTy(ElementVT))
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Prince781 wrote:

We want to bail out early if the elements being stored are legal non-packed vector types (i32, etc).

As for v4i8, I realize this won't get triggered because in the case of something like:

```mir
v: v4i8 = BUILD_VECTOR a, b, c, d
STORE v
```
The `BUILD_VECTOR` will be turned into a PRMT after legalization but before we hit this combiner rule. Rather than having `!isPackedVectorVy(ElementVT) || ElementVT == MVT::v4i8` I think it's better to leave this check as-is since it's not harmful and keeps the code looking cleaner.

https://github.com/llvm/llvm-project/pull/126337