[llvm] [AArch64] Align 0-cycle reg-mov model of GPR64, GPR32 reg classes (PR #146051)

[Tomer Shafir via llvm-commits]

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@@ -612,8 +612,11 @@ def FeatureExperimentalZeroingPseudos
 def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
   "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
 
-def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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tomershafir wrote:

yes, will push a fix

https://github.com/llvm/llvm-project/pull/146051