[llvm] [AArch64] Allow commuting the cmn if both sides of the comparison can be negated (PR #146233)
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Sat Jun 28 12:01:05 PDT 2025
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 09fbafdfb..3007089cb 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3446,7 +3446,8 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &DL,
}
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode &CC,
- const SDLoc &DL, AArch64CC::CondCode &OutCC, SelectionDAG &DAG) {
+ const SDLoc &DL, AArch64CC::CondCode &OutCC,
+ SelectionDAG &DAG) {
EVT VT = LHS.getValueType();
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
@@ -3976,8 +3977,8 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, LHS.getValueType(), LHS,
DAG.getValueType(MVT::i16));
Cmp = emitComparison(
- SExt, DAG.getSignedConstant(ValueofRHS, DL, RHS.getValueType()), CC, Arch64CC,
- DL, DAG);
+ SExt, DAG.getSignedConstant(ValueofRHS, DL, RHS.getValueType()), CC,
+ Arch64CC, DL, DAG);
}
}
``````````
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https://github.com/llvm/llvm-project/pull/146233
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