[llvm] [PowerPC] Use range-based for loops (NFC) (PR #146221)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 28 08:49:14 PDT 2025
https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/146221
None
>From 16259f746b39d015938b5234ab5d65855aaddb9f Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Fri, 27 Jun 2025 22:02:25 -0700
Subject: [PATCH] [PowerPC] Use range-based for loops (NFC)
---
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 20 ++++++-------
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 31 +++++++++-----------
2 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 15466ba9876cc..c0860fcdaa3b0 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2170,8 +2170,8 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
// The Floating-point register save area is right below the back chain word
// of the previous stack frame.
if (HasFPSaveArea) {
- for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
- int FI = FPRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &FPReg : FPRegs) {
+ int FI = FPReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
@@ -2219,18 +2219,18 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
if (HasGPSaveArea || HasG8SaveArea) {
// Move general register save area spill slots down, taking into account
// the size of the Floating-point register save area.
- for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
- if (!GPRegs[i].isSpilledToReg()) {
- int FI = GPRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &GPReg : GPRegs) {
+ if (!GPReg.isSpilledToReg()) {
+ int FI = GPReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
}
// Move general register save area spill slots down, taking into account
// the size of the Floating-point register save area.
- for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
- if (!G8Regs[i].isSpilledToReg()) {
- int FI = G8Regs[i].getFrameIdx();
+ for (const CalleeSavedInfo &G8Reg : G8Regs) {
+ if (!G8Reg.isSpilledToReg()) {
+ int FI = G8Reg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
}
@@ -2272,8 +2272,8 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
LowerBound &= ~(15);
- for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
- int FI = VRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &VReg : VRegs) {
+ int FI = VReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 88c6fe632d266..34500c70feaa5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -4445,11 +4445,11 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
// The fixed integer arguments of a variadic function are stored to the
// VarArgsFrameIndex on the stack so that they may be loaded by
// dereferencing the result of va_next.
- for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
+ for (MCPhysReg GPArgReg : GPArgRegs) {
// Get an existing live-in vreg, or add a new one.
- Register VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
+ Register VReg = MF.getRegInfo().getLiveInVirtReg(GPArgReg);
if (!VReg)
- VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
+ VReg = MF.addLiveIn(GPArgReg, &PPC::GPRCRegClass);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store =
@@ -4549,13 +4549,13 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
unsigned NumBytes = LinkageSize;
unsigned AvailableFPRs = Num_FPR_Regs;
unsigned AvailableVRs = Num_VR_Regs;
- for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
- if (Ins[i].Flags.isNest())
+ for (const ISD::InputArg &In : Ins) {
+ if (In.Flags.isNest())
continue;
- if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
- PtrByteSize, LinkageSize, ParamAreaSize,
- NumBytes, AvailableFPRs, AvailableVRs))
+ if (CalculateStackSlotUsed(In.VT, In.ArgVT, In.Flags, PtrByteSize,
+ LinkageSize, ParamAreaSize, NumBytes,
+ AvailableFPRs, AvailableVRs))
HasParameterArea = true;
}
@@ -5766,9 +5766,8 @@ buildCallOperands(SmallVectorImpl<SDValue> &Ops,
// Add argument registers to the end of the list so that they are known live
// into the call.
- for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
- Ops.push_back(DAG.getRegister(RegsToPass[i].first,
- RegsToPass[i].second.getValueType()));
+ for (const auto [Reg, N] : RegsToPass)
+ Ops.push_back(DAG.getRegister(Reg, N.getValueType()));
// We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
// no way to mark dependencies as implicit here.
@@ -6191,9 +6190,8 @@ SDValue PPCTargetLowering::LowerCall_32SVR4(
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InGlue;
- for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
- RegsToPass[i].second, InGlue);
+ for (const auto [Reg, N] : RegsToPass) {
+ Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue);
InGlue = Chain.getValue(1);
}
@@ -6805,9 +6803,8 @@ SDValue PPCTargetLowering::LowerCall_64SVR4(
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InGlue;
- for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
- RegsToPass[i].second, InGlue);
+ for (const auto [Reg, N] : RegsToPass) {
+ Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue);
InGlue = Chain.getValue(1);
}
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