[llvm] [NVPTX] support packed f32 instructions for sm_100+ (PR #126337)

[Alex MacLean via llvm-commits]

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@@ -5743,7 +5799,7 @@ static SDValue PerformVSELECTCombine(SDNode *N,
 static SDValue
 PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   auto VT = N->getValueType(0);
-  if (!DCI.isAfterLegalizeDAG() || !Isv2x16VT(VT))
+  if (!DCI.isAfterLegalizeDAG() || !isPackedVectorTy(VT) || !VT.is32BitVector())
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AlexMaclean wrote:

Will this include v4i8 where it did not previously? is this intentional?

https://github.com/llvm/llvm-project/pull/126337