[llvm] 375af75 - [RISCV] Simplify the check for when to call EmitLoweredCascadedSelect. NFC (#145930)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 27 08:56:53 PDT 2025


Author: Craig Topper
Date: 2025-06-27T08:56:49-07:00
New Revision: 375af75efb2ed24f17c1d261bc3c094cac644509

URL: https://github.com/llvm/llvm-project/commit/375af75efb2ed24f17c1d261bc3c094cac644509
DIFF: https://github.com/llvm/llvm-project/commit/375af75efb2ed24f17c1d261bc3c094cac644509.diff

LOG: [RISCV] Simplify the check for when to call EmitLoweredCascadedSelect. NFC (#145930)

Based on the comments and tests, we only want to call
EmitLoweredCascadedSelect on selects of FP registers.

Everytime we add a new branch with immediate opcode, we've been
excluding it here.

This patch switches to checking that the comparison operands are both
registers so branch on immediate is automatically excluded.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c1212a8b1cf17..4cf9075078eea 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21445,12 +21445,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   // EmitLoweredCascadedSelect.
 
   auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
-  if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
-       MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5_CV &&
-       MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC &&
-       MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC &&
-       MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC &&
-       MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC) &&
+  if (MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
+      MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
       Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
       Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
       Next->getOperand(5).isKill())


        


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