[llvm] [AArch64] Align 0-cycle reg-mov model of GPR64, GPR32 reg classes (PR #146051)

[David Green via llvm-commits]

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@@ -5063,8 +5063,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addImm(0)
           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     } else {
-      if (Subtarget.hasZeroCycleRegMove()) {
-        // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
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davemgreen wrote:

These comments would be good to keep, I think.

https://github.com/llvm/llvm-project/pull/146051