[llvm] [Xtensa] Implement THREADPTR and DFPAccel Xtensa Options. (PR #145543)

[Andrei Safronov via llvm-commits]

================
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=xtensa -mattr=+threadptr -disable-block-placement -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+ at i = external thread_local global i32
+
+define i32 @f() {
+; CHECK-LABEL: f:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    l32r a8, .LCPI0_0
+; CHECK-NEXT:    rur a9, threadptr
+; CHECK-NEXT:    add a8, a9, a8
+; CHECK-NEXT:    l32i a2, a8, 0
+; CHECK-NEXT:    ret
+entry:
+	%tmp1 = load i32, ptr @i
+	ret i32 %tmp1
----------------
andreisfr wrote:

Fixed

https://github.com/llvm/llvm-project/pull/145543