[llvm] [AArch64] Do not generate ld1IndexPost when inserting into lane 0 of a zero vector (PR #145723)

David Green via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 27 04:47:22 PDT 2025

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https://github.com/davemgreen closed https://github.com/llvm/llvm-project/pull/145723

Previous message: [llvm] [AArch64] Do not generate ld1IndexPost when inserting into lane 0 of a zero vector (PR #145723)
Next message: [llvm] [RFC][WIP][X86] Attempt to move the AVX512 VSELECT(COND, 0, X) -> VSELECT(!COND, X, 0) fold to DAGToDAG (PR #145724)
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