[llvm] [ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC) (PR #146061)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 27 04:23:59 PDT 2025
https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/146061
None
>From 382143f2fc311aa604cbf84af8b6c126cc91df3a Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Fri, 27 Jun 2025 12:05:38 +0100
Subject: [PATCH] [ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC)
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 46 ++++++++++-----------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c1212a8b1cf17..8cfc28ead18fb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6848,32 +6848,32 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG,
SDLoc DL(Op);
// Get sign bit into an integer value.
- SDValue SignAsInt;
unsigned SignSize = Sign.getValueSizeInBits();
- if (SignSize == Subtarget.getXLen()) {
- SignAsInt = DAG.getNode(ISD::BITCAST, DL, XLenVT, Sign);
- } else if (SignSize == 16) {
- SignAsInt = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Sign);
- } else if (SignSize == 32) {
- SignAsInt = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenVT, Sign);
- } else if (SignSize == 64) {
- assert(XLenVT == MVT::i32 && "Unexpected type");
- // Copy the upper word to integer.
- SignAsInt = DAG.getNode(RISCVISD::SplitF64, DL, {MVT::i32, MVT::i32}, Sign)
- .getValue(1);
- SignSize = 32;
- } else
- llvm_unreachable("Unexpected sign size");
+ SDValue SignAsInt = [&]() {
+ if (SignSize == Subtarget.getXLen())
+ return DAG.getNode(ISD::BITCAST, DL, XLenVT, Sign);
+ switch (SignSize) {
+ case 16:
+ return DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Sign);
+ case 32:
+ return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenVT, Sign);
+ case 64: {
+ assert(XLenVT == MVT::i32 && "Unexpected type");
+ // Copy the upper word to integer.
+ SignSize = 32;
+ return DAG.getNode(RISCVISD::SplitF64, DL, {MVT::i32, MVT::i32}, Sign)
+ .getValue(1);
+ }
+ default:
+ llvm_unreachable("Unexpected sign size");
+ }
+ }();
// Get the signbit at the right position for MagAsInt.
- int ShiftAmount = (int)SignSize - (int)Mag.getValueSizeInBits();
- if (ShiftAmount > 0) {
- SignAsInt = DAG.getNode(ISD::SRL, DL, XLenVT, SignAsInt,
- DAG.getConstant(ShiftAmount, DL, XLenVT));
- } else if (ShiftAmount < 0) {
- SignAsInt = DAG.getNode(ISD::SHL, DL, XLenVT, SignAsInt,
- DAG.getConstant(-ShiftAmount, DL, XLenVT));
- }
+ if (int ShiftAmount = (int)SignSize - (int)Mag.getValueSizeInBits())
+ SignAsInt = DAG.getNode(ShiftAmount > 0 ? ISD::SRL : ISD::SHL, DL, XLenVT,
+ SignAsInt,
+ DAG.getConstant(std::abs(ShiftAmount), DL, XLenVT));
// Mask the sign bit and any bits above it. The extra bits will be dropped
// when we convert back to FP.
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