[llvm] [AArch64] Fix #94909: Optimize vector fmul(sitofp(x), 0.5) -> scvtf(x, 2) (PR #141480)

[David Green via llvm-commits]

================
@@ -3952,6 +3960,132 @@ static bool checkCVTFixedPointOperandWithFBits(SelectionDAG *CurDAG, SDValue N,
   return true;
 }
 
+static bool checkCVTFixedPointOperandWithFBitsForVectors(SelectionDAG *CurDAG,
+                                                         SDValue N,
+                                                         SDValue &FixedPos,
+                                                         unsigned FloatWidth,
+                                                         bool IsReciprocal) {
+
+  SDValue ImmediateNode;
+  // N must be a bitcast, nvcast, or fmov
+  if (N.getOpcode() == ISD::BITCAST || N.getOpcode() == AArch64ISD::NVCAST ||
+      N.getOpcode() == AArch64ISD::FMOV) {
+    ImmediateNode = N.getOperand(0);
----------------
davemgreen wrote:

I would suggest that this be a little tighter on what it considers, to prevent any (rare) cases from treating the node with an incorrect type (like looking at operand 0 where it doesn't exist and how FMOV is currently handled.

I would probably make it something like
```
SDValue ImmediateNode = N;
if (N.getOpcode() == ISD::BITCAST || N.getOpcode() == AArch64ISD::NVCAST)
  ImmediateNode = N.getOperand(0);
```

Then check the node type is still a vector (in case it is bitcast to a scalar) `ImmediateNode.getValueType().isVector()`. 
The if below would check `ImmediateNode.getOpcode() == AArch64ISD::FMOV`, not for ISD::Constant, and check its operand (which we know should always be a ConstantSDNode.

That should hopefully make it more resilient to odd cases that don't come up very often, and hopefully a little more clear which nodes equate to what.

https://github.com/llvm/llvm-project/pull/141480