[llvm] [WebAssembly] [Backend] Wasm optimize illegal bitmask (PR #145627)

Sam Parker via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 27 00:33:39 PDT 2025


================
@@ -3236,6 +3244,57 @@ static SDValue performBitcastCombine(SDNode *N,
         DL, VT);
   }
 
+  // bitcast <N x i1>(setcc ...) to concat iN, where N = 32 and 64 (illegal)
+  if (NumElts == 32 || NumElts == 64) {
+    // Strategy: We will setcc them seperately in v16i1
+    // Bitcast them to i16, extend them to either i32 or i64.
+    // Add them together, shifting left 1 by 1.
+    SDValue Concat, SetCCVector;
+    ISD::CondCode SetCond;
+
+    if (!sd_match(N, m_BitCast(m_c_SetCC(m_Value(Concat),
+                                         m_VectorVT(m_Value(SetCCVector)),
+                                         m_CondCode(SetCond)))))
+      return SDValue();
+    // COMMITTED at this point, SDValue() if match fails.
+    if (Concat.getOpcode() != ISD::CONCAT_VECTORS)
+      return SDValue();
+    // CHECK IF VECTOR is a constant, i.e all values are the same
+    if (!ISD::isBuildVectorOfConstantSDNodes(SetCCVector.getNode()))
+      return SDValue();
+
+    SmallVector<SDValue> Vec;
+    for (SDValue Const : SetCCVector->ops()) {
+      Vec.push_back(Const);
+      if (Vec.size() >= 16)
+        break;
+    }
+
+    // Build our own version of splat Vector.
+    SDValue SplitSetCCVec = DAG.getBuildVector(MVT::v16i8, DL, Vec);
+
+    SmallVector<SDValue> VectorsToShuffle;
+    for (SDValue V : Concat->ops())
+      VectorsToShuffle.push_back(DAG.getBitcast(
+          MVT::i16, DAG.getSetCC(DL, MVT::v16i1, V, SplitSetCCVec, SetCond)));
+
+    MVT ReturnType = VectorsToShuffle.size() == 2 ? MVT::i32 : MVT::i64;
+    SDValue ReturningInteger = DAG.getConstant(0, DL, ReturnType);
+
+    for (SDValue V : VectorsToShuffle) {
+      ReturningInteger = DAG.getNode(
+          ISD::SHL, DL, ReturnType,
+          {DAG.getShiftAmountConstant(16, ReturnType, DL), ReturningInteger});
+
+      SDValue ExtendedV = DAG.getZExtOrTrunc(V, DL, ReturnType);
+      ReturningInteger =
+          DAG.getNode(ISD::ADD, DL, ReturnType, {ReturningInteger, ExtendedV});
+    }
+
+    // ReturningInteger->print(llvm::errs());
----------------
sparker-arm wrote:

nit: left over debug code?

https://github.com/llvm/llvm-project/pull/145627


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