[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[via llvm-commits]

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@@ -18,11 +18,11 @@ define <2 x i32> @test_add2x32(ptr %a_ptr, ptr %b_ptr) {
 ; CHECK-LABEL: test_add2x32:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    flat_load_dword v4, v[2:3]
-; CHECK-NEXT:    flat_load_dword v5, v[0:1]
-; CHECK-NEXT:    v_mov_b32_e32 v1, 48
+; CHECK-NEXT:    flat_load_dwordx2 v[4:5], v[0:1]
+; CHECK-NEXT:    flat_load_dwordx2 v[6:7], v[2:3]
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_or_b32_e32 v0, v5, v4
+; CHECK-NEXT:    v_or_b32_e32 v1, v5, v7
+; CHECK-NEXT:    v_or_b32_e32 v0, v4, v6
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LU-JOHN wrote:

The purpose of this test was to ensure range metadata is being utilized.  The fact that the source add has been converted to a V_MOV instruction or a V_OR instruction shows that the range metadata is being used.  So these new results still pass the original intent of the test.   

Ideally, though all the results should be a V_MOV and there would be no V_OR instructions.  

Perhaps the comment should be updated to:

; Ensure that range metadata is handled correctly for vector loads by checking that add instructions have
; been converted to V_MOV or V_ADD instructions.  Since the range metadata constrains the range to a single value
; all the tests would ideally generate V_MOV instructions.

https://github.com/llvm/llvm-project/pull/140694