[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (PR #145643)

[Craig Topper via llvm-commits]

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@@ -1469,6 +1477,20 @@ def: Pat<(i32 (ctlz (not (i32 GPR:$rs1)))), (QC_CLO GPR:$rs1)>;
 let Predicates = [HasVendorXqciint, IsRV32] in
 def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
 
+let Predicates = [HasVendorXqcicm, IsRV32] in {
+def : Pat<(select (XLenVT GPRNoX0:$cond), (XLenVT GPRNoX0:$a),(XLenVT GPRNoX0:$b)),
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topperc wrote:

Please name the operands $rd, $rs1, etc. here

https://github.com/llvm/llvm-project/pull/145643