[llvm] 8a65196 - [RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 26 09:54:31 PDT 2025
Author: Craig Topper
Date: 2025-06-26T09:46:14-07:00
New Revision: 8a6519677c08946c1d1d526226c58df1bd4597bd
URL: https://github.com/llvm/llvm-project/commit/8a6519677c08946c1d1d526226c58df1bd4597bd
DIFF: https://github.com/llvm/llvm-project/commit/8a6519677c08946c1d1d526226c58df1bd4597bd.diff
LOG: [RISCV] Move CascadeSelect test into float/half/double-select-fcmp.ll. NFC
We only had a test for the F extension before. This increases
coverage to D, Zfh, Zfhmin, Finx, Dinx, Zhinx.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/test/CodeGen/RISCV/float-select-fcmp.ll
llvm/test/CodeGen/RISCV/half-select-fcmp.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index e7ff991413013..1deea55b083ce 100644
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -638,3 +638,48 @@ define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
%2 = select i1 %1, i32 1, i32 2
ret i32 %2
}
+
+define double @CascadedSelect(double noundef %a) {
+; CHECKRV32ZDINX-LABEL: CascadedSelect:
+; CHECKRV32ZDINX: # %bb.0: # %entry
+; CHECKRV32ZDINX-NEXT: lui a3, %hi(.LCPI20_0)
+; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI20_0)(a3)
+; CHECKRV32ZDINX-NEXT: addi a3, a3, %lo(.LCPI20_0)
+; CHECKRV32ZDINX-NEXT: lw a3, 4(a3)
+; CHECKRV32ZDINX-NEXT: flt.d a4, a2, a0
+; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3
+; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
+; CHECKRV32ZDINX-NEXT: flt.d a4, a0, zero
+; CHECKRV32ZDINX-NEXT: li a2, 0
+; CHECKRV32ZDINX-NEXT: li a3, 0
+; CHECKRV32ZDINX-NEXT: bnez a4, .LBB20_3
+; CHECKRV32ZDINX-NEXT: # %bb.2: # %entry
+; CHECKRV32ZDINX-NEXT: mv a2, a0
+; CHECKRV32ZDINX-NEXT: mv a3, a1
+; CHECKRV32ZDINX-NEXT: .LBB20_3: # %entry
+; CHECKRV32ZDINX-NEXT: mv a0, a2
+; CHECKRV32ZDINX-NEXT: mv a1, a3
+; CHECKRV32ZDINX-NEXT: ret
+;
+; CHECKRV64ZDINX-LABEL: CascadedSelect:
+; CHECKRV64ZDINX: # %bb.0: # %entry
+; CHECKRV64ZDINX-NEXT: li a1, 1023
+; CHECKRV64ZDINX-NEXT: slli a1, a1, 52
+; CHECKRV64ZDINX-NEXT: flt.d a2, a1, a0
+; CHECKRV64ZDINX-NEXT: bnez a2, .LBB20_3
+; CHECKRV64ZDINX-NEXT: # %bb.1: # %entry
+; CHECKRV64ZDINX-NEXT: flt.d a2, a0, zero
+; CHECKRV64ZDINX-NEXT: li a1, 0
+; CHECKRV64ZDINX-NEXT: bnez a2, .LBB20_3
+; CHECKRV64ZDINX-NEXT: # %bb.2: # %entry
+; CHECKRV64ZDINX-NEXT: mv a1, a0
+; CHECKRV64ZDINX-NEXT: .LBB20_3: # %entry
+; CHECKRV64ZDINX-NEXT: mv a0, a1
+; CHECKRV64ZDINX-NEXT: ret
+entry:
+ %cmp = fcmp ogt double %a, 1.000000e+00
+ %cmp1 = fcmp olt double %a, 0.000000e+00
+ %.a = select i1 %cmp1, double 0.000000e+00, double %a
+ %retval.0 = select i1 %cmp, double 1.000000e+00, double %.a
+ ret double %retval.0
+}
diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index a2ff0d33e2d31..f08777ac3e5de 100644
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -451,3 +451,42 @@ define signext i32 @select_fcmp_uge_1_2(float %a, float %b) nounwind {
%2 = select i1 %1, i32 1, i32 2
ret i32 %2
}
+
+define float @CascadedSelect(float noundef %a) {
+; CHECK-LABEL: CascadedSelect:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: flt.s a0, fa5, fa0
+; CHECK-NEXT: bnez a0, .LBB20_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmv.w.x fa5, zero
+; CHECK-NEXT: flt.s a0, fa0, fa5
+; CHECK-NEXT: bnez a0, .LBB20_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmv.s fa5, fa0
+; CHECK-NEXT: .LBB20_3: # %entry
+; CHECK-NEXT: fmv.s fa0, fa5
+; CHECK-NEXT: ret
+;
+; CHECKZFINX-LABEL: CascadedSelect:
+; CHECKZFINX: # %bb.0: # %entry
+; CHECKZFINX-NEXT: lui a1, 260096
+; CHECKZFINX-NEXT: flt.s a2, a1, a0
+; CHECKZFINX-NEXT: bnez a2, .LBB20_3
+; CHECKZFINX-NEXT: # %bb.1: # %entry
+; CHECKZFINX-NEXT: flt.s a2, a0, zero
+; CHECKZFINX-NEXT: li a1, 0
+; CHECKZFINX-NEXT: bnez a2, .LBB20_3
+; CHECKZFINX-NEXT: # %bb.2: # %entry
+; CHECKZFINX-NEXT: mv a1, a0
+; CHECKZFINX-NEXT: .LBB20_3: # %entry
+; CHECKZFINX-NEXT: mv a0, a1
+; CHECKZFINX-NEXT: ret
+entry:
+ %cmp = fcmp ogt float %a, 1.000000e+00
+ %cmp1 = fcmp olt float %a, 0.000000e+00
+ %.a = select i1 %cmp1, float 0.000000e+00, float %a
+ %retval.0 = select i1 %cmp, float 1.000000e+00, float %.a
+ ret float %retval.0
+}
diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index d92dcb9eac4c6..bf535b1cbd084 100644
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -874,3 +874,87 @@ define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
%2 = select i1 %1, i32 1, i32 2
ret i32 %2
}
+
+define half @CascadedSelect(half noundef %a) {
+; CHECK-LABEL: CascadedSelect:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
+; CHECK-NEXT: flt.h a0, fa5, fa0
+; CHECK-NEXT: bnez a0, .LBB20_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmv.h.x fa5, zero
+; CHECK-NEXT: flt.h a0, fa0, fa5
+; CHECK-NEXT: bnez a0, .LBB20_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmv.h fa5, fa0
+; CHECK-NEXT: .LBB20_3: # %entry
+; CHECK-NEXT: fmv.h fa0, fa5
+; CHECK-NEXT: ret
+;
+; CHECKIZHINX-LABEL: CascadedSelect:
+; CHECKIZHINX: # %bb.0: # %entry
+; CHECKIZHINX-NEXT: li a1, 15
+; CHECKIZHINX-NEXT: slli a1, a1, 10
+; CHECKIZHINX-NEXT: flt.h a2, a1, a0
+; CHECKIZHINX-NEXT: bnez a2, .LBB20_3
+; CHECKIZHINX-NEXT: # %bb.1: # %entry
+; CHECKIZHINX-NEXT: flt.h a2, a0, zero
+; CHECKIZHINX-NEXT: li a1, 0
+; CHECKIZHINX-NEXT: bnez a2, .LBB20_3
+; CHECKIZHINX-NEXT: # %bb.2: # %entry
+; CHECKIZHINX-NEXT: mv a1, a0
+; CHECKIZHINX-NEXT: .LBB20_3: # %entry
+; CHECKIZHINX-NEXT: mv a0, a1
+; CHECKIZHINX-NEXT: ret
+;
+; CHECKIZFHMIN-LABEL: CascadedSelect:
+; CHECKIZFHMIN: # %bb.0: # %entry
+; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI20_0)
+; CHECKIZFHMIN-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa3, fa5
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
+; CHECKIZFHMIN-NEXT: bnez a0, .LBB20_3
+; CHECKIZFHMIN-NEXT: # %bb.1: # %entry
+; CHECKIZFHMIN-NEXT: fmv.w.x fa5, zero
+; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
+; CHECKIZFHMIN-NEXT: bnez a0, .LBB20_4
+; CHECKIZFHMIN-NEXT: # %bb.2: # %entry
+; CHECKIZFHMIN-NEXT: fmv.s fa5, fa0
+; CHECKIZFHMIN-NEXT: .LBB20_3: # %entry
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa5
+; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: .LBB20_4:
+; CHECKIZFHMIN-NEXT: fmv.h.x fa0, zero
+; CHECKIZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: CascadedSelect:
+; CHECKIZHINXMIN: # %bb.0: # %entry
+; CHECKIZHINXMIN-NEXT: mv a1, a0
+; CHECKIZHINXMIN-NEXT: li a0, 0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: lui a3, 260096
+; CHECKIZHINXMIN-NEXT: flt.s a4, a2, zero
+; CHECKIZHINXMIN-NEXT: flt.s a2, a3, a2
+; CHECKIZHINXMIN-NEXT: beqz a4, .LBB20_3
+; CHECKIZHINXMIN-NEXT: # %bb.1: # %entry
+; CHECKIZHINXMIN-NEXT: bnez a2, .LBB20_4
+; CHECKIZHINXMIN-NEXT: .LBB20_2: # %entry
+; CHECKIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
+; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: .LBB20_3: # %entry
+; CHECKIZHINXMIN-NEXT: mv a0, a1
+; CHECKIZHINXMIN-NEXT: beqz a2, .LBB20_2
+; CHECKIZHINXMIN-NEXT: .LBB20_4:
+; CHECKIZHINXMIN-NEXT: li a0, 15
+; CHECKIZHINXMIN-NEXT: slli a0, a0, 10
+; CHECKIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10
+; CHECKIZHINXMIN-NEXT: ret
+entry:
+ %cmp = fcmp ogt half %a, 1.000000e+00
+ %cmp1 = fcmp olt half %a, 0.000000e+00
+ %.a = select i1 %cmp1, half 0.000000e+00, half %a
+ %retval.0 = select i1 %cmp, half 1.000000e+00, half %.a
+ ret half %retval.0
+}
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index 005a01bf1000a..4066f62afad0a 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -338,45 +338,3 @@ entry:
%ret = add i32 %cond1, %cond2
ret i32 %ret
}
-
-define float @CascadedSelect(float noundef %a) {
-; RV32I-LABEL: CascadedSelect:
-; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: fmv.w.x fa5, a0
-; RV32I-NEXT: lui a0, 260096
-; RV32I-NEXT: fmv.w.x fa4, a0
-; RV32I-NEXT: flt.s a0, fa4, fa5
-; RV32I-NEXT: bnez a0, .LBB8_3
-; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: fmv.w.x fa4, zero
-; RV32I-NEXT: flt.s a0, fa5, fa4
-; RV32I-NEXT: bnez a0, .LBB8_3
-; RV32I-NEXT: # %bb.2: # %entry
-; RV32I-NEXT: fmv.s fa4, fa5
-; RV32I-NEXT: .LBB8_3: # %entry
-; RV32I-NEXT: fmv.x.w a0, fa4
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: CascadedSelect:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: fmv.w.x fa5, a0
-; RV64I-NEXT: lui a0, 260096
-; RV64I-NEXT: fmv.w.x fa4, a0
-; RV64I-NEXT: flt.s a0, fa4, fa5
-; RV64I-NEXT: bnez a0, .LBB8_3
-; RV64I-NEXT: # %bb.1: # %entry
-; RV64I-NEXT: fmv.w.x fa4, zero
-; RV64I-NEXT: flt.s a0, fa5, fa4
-; RV64I-NEXT: bnez a0, .LBB8_3
-; RV64I-NEXT: # %bb.2: # %entry
-; RV64I-NEXT: fmv.s fa4, fa5
-; RV64I-NEXT: .LBB8_3: # %entry
-; RV64I-NEXT: fmv.x.w a0, fa4
-; RV64I-NEXT: ret
-entry:
- %cmp = fcmp ogt float %a, 1.000000e+00
- %cmp1 = fcmp olt float %a, 0.000000e+00
- %.a = select i1 %cmp1, float 0.000000e+00, float %a
- %retval.0 = select i1 %cmp, float 1.000000e+00, float %.a
- ret float %retval.0
-}
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