[llvm] [MergeICmps] Fix miss-compile in MergeICmps in presence of blockaddresses (PR #145925)
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Thu Jun 26 09:42:17 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: None (Ralender)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/145925.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Scalar/MergeICmps.cpp (+4)
- (added) llvm/test/Transforms/MergeICmps/X86/blockaddresses.ll (+87)
``````````diff
diff --git a/llvm/lib/Transforms/Scalar/MergeICmps.cpp b/llvm/lib/Transforms/Scalar/MergeICmps.cpp
index 4291f3aee0cd1..a83cbd17a70dc 100644
--- a/llvm/lib/Transforms/Scalar/MergeICmps.cpp
+++ b/llvm/lib/Transforms/Scalar/MergeICmps.cpp
@@ -479,6 +479,10 @@ BCECmpChain::BCECmpChain(const std::vector<BasicBlock *> &Blocks, PHINode &Phi,
BaseIdentifier BaseId;
for (BasicBlock *const Block : Blocks) {
assert(Block && "invalid block");
+ if (Block->hasAddressTaken()) {
+ LLVM_DEBUG(dbgs() << "cannot merge blocks with blockaddress\n");
+ return;
+ }
std::optional<BCECmpBlock> Comparison = visitCmpBlock(
Phi.getIncomingValueForBlock(Block), Block, Phi.getParent(), BaseId);
if (!Comparison) {
diff --git a/llvm/test/Transforms/MergeICmps/X86/blockaddresses.ll b/llvm/test/Transforms/MergeICmps/X86/blockaddresses.ll
new file mode 100644
index 0000000000000..d8f47a1d080f4
--- /dev/null
+++ b/llvm/test/Transforms/MergeICmps/X86/blockaddresses.ll
@@ -0,0 +1,87 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=mergeicmps -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%type = type { i64, i64, i64, i64 }
+
+define fastcc i1 @test(ptr byval(%type) %a, ptr byval(%type) %b, i1 %cond) {
+; CHECK-LABEL: define fastcc i1 @test(
+; CHECK-SAME: ptr byval([[TYPE:%.*]]) [[A:%.*]], ptr byval([[TYPE]]) [[B:%.*]], i1 [[COND:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[VALUE401:%.*]] = select i1 [[COND]], ptr blockaddress(@test, %[[BLOCK307:.*]]), ptr blockaddress(@test, %[[EXIT:.*]])
+; CHECK-NEXT: indirectbr ptr [[VALUE401]], [label %[[BLOCK307]], label %exit]
+; CHECK: [[BLOCK307]]:
+; CHECK-NEXT: [[VALUE403:%.*]] = load i64, ptr [[A]], align 8
+; CHECK-NEXT: [[VALUE404:%.*]] = load i64, ptr [[A]], align 8
+; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i64 [[VALUE403]], [[VALUE404]]
+; CHECK-NEXT: br i1 [[CMP_I]], label %[[LAND_LHS_TRUE_I:.*]], label %[[TEST_EXIT:.*]]
+; CHECK: [[LAND_LHS_TRUE_I]]:
+; CHECK-NEXT: [[B_I:%.*]] = getelementptr [[TYPE]], ptr [[A]], i64 0, i32 0
+; CHECK-NEXT: [[VALUE405:%.*]] = load i64, ptr [[B_I]], align 8
+; CHECK-NEXT: [[B3_I:%.*]] = getelementptr [[TYPE]], ptr [[B]], i64 0, i32 0
+; CHECK-NEXT: [[VALUE406:%.*]] = load i64, ptr [[B3_I]], align 8
+; CHECK-NEXT: [[CMP4_I:%.*]] = icmp eq i64 [[VALUE405]], [[VALUE406]]
+; CHECK-NEXT: br i1 [[CMP4_I]], label %[[LAND_LHS_TRUE5_I:.*]], label %[[TEST_EXIT]]
+; CHECK: [[LAND_LHS_TRUE5_I]]:
+; CHECK-NEXT: [[C_I:%.*]] = getelementptr [[TYPE]], ptr [[A]], i64 0, i32 2
+; CHECK-NEXT: [[VALUE407:%.*]] = load i64, ptr [[C_I]], align 8
+; CHECK-NEXT: [[C6_I:%.*]] = getelementptr [[TYPE]], ptr [[B]], i64 0, i32 2
+; CHECK-NEXT: [[VALUE408:%.*]] = load i64, ptr [[C6_I]], align 8
+; CHECK-NEXT: [[CMP7_I:%.*]] = icmp eq i64 [[VALUE407]], [[VALUE408]]
+; CHECK-NEXT: br i1 [[CMP7_I]], label %[[LAND_RHS_I:.*]], label %[[TEST_EXIT]]
+; CHECK: [[LAND_RHS_I]]:
+; CHECK-NEXT: [[D_I:%.*]] = getelementptr [[TYPE]], ptr [[A]], i64 0, i32 3
+; CHECK-NEXT: [[VALUE409:%.*]] = load i64, ptr [[D_I]], align 8
+; CHECK-NEXT: [[D8_I:%.*]] = getelementptr [[TYPE]], ptr [[B]], i64 0, i32 3
+; CHECK-NEXT: [[VALUE410:%.*]] = load i64, ptr [[D8_I]], align 8
+; CHECK-NEXT: [[CMP9_I:%.*]] = icmp eq i64 [[VALUE409]], [[VALUE410]]
+; CHECK-NEXT: br label %[[TEST_EXIT]]
+; CHECK: [[TEST_EXIT]]:
+; CHECK-NEXT: [[VALUE411:%.*]] = phi i1 [ false, %[[LAND_LHS_TRUE5_I]] ], [ false, %[[LAND_LHS_TRUE_I]] ], [ false, %[[BLOCK307]] ], [ [[CMP9_I]], %[[LAND_RHS_I]] ]
+; CHECK-NEXT: ret i1 false
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %Value401 = select i1 %cond, ptr blockaddress(@test, %Block307), ptr blockaddress(@test, %exit)
+ indirectbr ptr %Value401, [label %Block307, label %exit]
+
+Block307: ; preds = %entry
+ %Value403 = load i64, ptr %a, align 8
+ %Value404 = load i64, ptr %a, align 8
+ %cmp.i = icmp eq i64 %Value403, %Value404
+ br i1 %cmp.i, label %land.lhs.true.i, label %test.exit
+
+land.lhs.true.i: ; preds = %Block307
+ %b.i = getelementptr %type, ptr %a, i64 0, i32 0
+ %Value405 = load i64, ptr %b.i, align 8
+ %b3.i = getelementptr %type, ptr %b, i64 0, i32 0
+ %Value406 = load i64, ptr %b3.i, align 8
+ %cmp4.i = icmp eq i64 %Value405, %Value406
+ br i1 %cmp4.i, label %land.lhs.true5.i, label %test.exit
+
+land.lhs.true5.i: ; preds = %land.lhs.true.i
+ %c.i = getelementptr %type, ptr %a, i64 0, i32 2
+ %Value407 = load i64, ptr %c.i, align 8
+ %c6.i = getelementptr %type, ptr %b, i64 0, i32 2
+ %Value408 = load i64, ptr %c6.i, align 8
+ %cmp7.i = icmp eq i64 %Value407, %Value408
+ br i1 %cmp7.i, label %land.rhs.i, label %test.exit
+
+land.rhs.i: ; preds = %land.lhs.true5.i
+ %d.i = getelementptr %type, ptr %a, i64 0, i32 3
+ %Value409 = load i64, ptr %d.i, align 8
+ %d8.i = getelementptr %type, ptr %b, i64 0, i32 3
+ %Value410 = load i64, ptr %d8.i, align 8
+ %cmp9.i = icmp eq i64 %Value409, %Value410
+ br label %test.exit
+
+test.exit: ; preds = %land.rhs.i, %land.lhs.true5.i, %land.lhs.true.i, %Block307
+ %Value411 = phi i1 [ false, %land.lhs.true5.i ], [ false, %land.lhs.true.i ], [ false, %Block307 ], [ %cmp9.i, %land.rhs.i ]
+ ret i1 false
+
+exit: ; preds = %entry
+ ret i1 false
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/145925
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