[llvm] [RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (PR #145147)

[Craig Topper via llvm-commits]

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@@ -1400,6 +1424,12 @@ bool RISCVInstrInfo::reverseBranchCondition(
   case RISCV::QC_E_BLTUI:
     Cond[0].setImm(RISCV::QC_E_BGEUI);
     break;
+  case RISCV::NDS_BBC:
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topperc wrote:

Do we need to add BEQC/BNEC here?

https://github.com/llvm/llvm-project/pull/145147