[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #144620)
Arjun Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 25 21:55:47 PDT 2025
https://github.com/arjunUpatel updated https://github.com/llvm/llvm-project/pull/144620
>From 52ebb65f8c0879a7e75295b3c3aae9acaeb5d57e Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Tue, 10 Jun 2025 19:33:37 -0400
Subject: [PATCH 01/13] Remove changes affecting non-RISCV targets
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 5 +
llvm/lib/MC/MCInstrAnalysis.cpp | 6 +
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 113 ++++++++++++++++--
.../tools/llvm-objdump/RISCV/Inputs/riscv-ar | Bin 0 -> 1062552 bytes
.../RISCV/Inputs/riscv-ar-coverage | Bin 0 -> 1058216 bytes
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 +
.../llvm-objdump/RISCV/riscv-ar-coverage.s | 111 +++++++++++++++++
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 57 +++++++++
llvm/tools/llvm-objdump/llvm-objdump.cpp | 11 +-
9 files changed, 290 insertions(+), 15 deletions(-)
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 63a4e02a92360..1f05e8546c3d1 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -182,6 +182,11 @@ class LLVM_ABI MCInstrAnalysis {
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;
+ /// Given an instruction that accesses a memory address, try to compute
+ /// the target address. Return true on success, and the address in \p Target.
+ virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size, uint64_t &Target) const;
+
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
virtual std::optional<uint64_t>
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index cea905d092e0b..1ae0c91a2590c 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -30,6 +30,12 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
return false;
}
+bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size,
+ uint64_t &Target) const {
+ return false;
+}
+
std::optional<uint64_t> MCInstrAnalysis::evaluateMemoryOperandAddress(
const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
uint64_t Size) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index f3b93f032588c..e52f5e50832c7 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -29,7 +29,9 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include <bitset>
+#include <cstdint>
#define GET_INSTRINFO_MC_DESC
#define ENABLE_INSTR_PREDICATE_VERIFIER
@@ -129,6 +131,7 @@ namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
+ unsigned int ArchRegWidth;
static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -165,8 +168,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
- : MCInstrAnalysis(Info) {}
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, unsigned int ArchRegWidth)
+ : MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
void resetState() override { GPRValidMask.reset(); }
@@ -182,6 +185,17 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
+ case RISCV::C_LUI:
+ case RISCV::LUI: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ case RISCV::AUIPC: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
default: {
// Clear the state of all defined registers for instructions that we don't
// explicitly support.
@@ -193,10 +207,6 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
break;
}
- case RISCV::AUIPC:
- setGPRState(Inst.getOperand(0).getReg(),
- Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
- break;
}
}
@@ -234,6 +244,83 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
return false;
}
+ bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const override {
+ switch(Inst.getOpcode()) {
+ default:
+ return false;
+ case RISCV::C_ADDI:
+ case RISCV::ADDI: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target &= maskTrailingOnes<uint64_t>(ArchRegWidth);
+ return true;
+ }
+ break;
+ }
+ case RISCV::C_ADDIW:
+ case RISCV::ADDIW: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target = SignExtend64<32>(Target);
+ return true;
+ }
+ break;
+ }
+ case RISCV::LB:
+ case RISCV::LH:
+ case RISCV::LD:
+ case RISCV::LW:
+ case RISCV::LBU:
+ case RISCV::LHU:
+ case RISCV::LWU:
+ case RISCV::SB:
+ case RISCV::SH:
+ case RISCV::SW:
+ case RISCV::SD:
+ case RISCV::FLH:
+ case RISCV::FLW:
+ case RISCV::FLD:
+ case RISCV::FSH:
+ case RISCV::FSW:
+ case RISCV::FSD:
+ case RISCV::C_LD:
+ case RISCV::C_SD:
+ case RISCV::C_FLD:
+ case RISCV::C_FSD:
+ case RISCV::C_SW:
+ case RISCV::C_LW:
+ case RISCV::C_FSW:
+ case RISCV::C_FLW:
+ case RISCV::C_LBU:
+ case RISCV::C_LH:
+ case RISCV::C_LHU:
+ case RISCV::C_SB:
+ case RISCV::C_SH:
+ case RISCV::C_LWSP:
+ case RISCV::C_SWSP:
+ case RISCV::C_LDSP:
+ case RISCV::C_SDSP:
+ case RISCV::C_FLWSP:
+ case RISCV::C_FSWSP:
+ case RISCV::C_FLDSP:
+ case RISCV::C_FSDSP: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
+ }
+ break;
+ }
+ }
+ return false;
+ }
+
bool isTerminator(const MCInst &Inst) const override {
if (MCInstrAnalysis::isTerminator(Inst))
return true;
@@ -327,8 +414,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
} // end anonymous namespace
-static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info);
+static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 32);
+}
+
+static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 64);
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
@@ -344,12 +435,14 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
TargetRegistry::RegisterObjectTargetStreamer(
*T, createRISCVObjectTargetStreamer);
- TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
-
// Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
}
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(),
+ createRISCV32InstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(),
+ createRISCV64InstrAnalysis);
}
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
new file mode 100644
index 0000000000000000000000000000000000000000..bc335bc24f88d8577308802b27dbded31834a89f
GIT binary patch
literal 1062552
zcmeI$&ubk;902fX)2G!I8Z9-&ibR at v5g$oxZPB7BRz;|aVnI*gH7`vbHa~cIDXk(F
zu?NMo;z98!c*#ZR(W8HWUd4-eRYVbl#+lujG}%-sNWsHr;q7<!JM*2H{p?gQ?>>9x
zxt%+9gmMjq-$L~?TxX_o$Lo`Iq7|Q~!ilga-tP(f!X5E>SCy*=PSqjy*4O;bt#NnG
z55<`3zRdm2SjLrDc9>$S`={%hG;zF24Ea4$UD|tjZpQhXD6#aXy7Z1=G*8rsIlFD%
zjk at tXq7lnGlvvhF991sAM`*;gw3m35SbSdnY0$0e8v85zZtgSfFI}(1y6XMv$6LOq
zwbE}bf4^otm}e at n+FQ)U*IBM=i$@+;!pYnyvF!6gx4p8|o~YJL at 0?hkf9Y)a?z6L>
zp8oUey`{bxQ+ at f}-|URf59VBP{A+!EDWzgfl^V<a*YbBb+!%kP at mwsw%`SU#e{rbJ
zV9c%M`R>mB<voADUa$XSuFu`u!tU~&xAjO6AV7cs0RjXF5FkL{<^m%JhQrXYt6}8G
zaM<6vx?aat6^D*oy*|=P`Db^168{JF=PO?fjSLNkxo~*s_}QcP9%@~kJH9#=4z<4j
z at Tu1R)`1Tu<Nf=u(*5 at zPR$;VweK9e`MR<M2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+0D)T<c<;)sk2R720RjXF5FkK+009C72oSg}0z-M$
z@!{Jty-5iWAV7cs0RjXF5FkK+0D=F9z^NzWKKi|tnTuh^L~OSD7au>`n_QllUYJ}S
zpYEjA`N`$U>2A8sq}*G*nU#KQgfqRxH)s1#jGj4jdUWDMd!l{f-`{CR)xA4}#-AJR
zsPcP4X#5>wZyw(r-db>P&Yx at KM>g_RW8?O~Mt<u&59NGw{)eml_We9k<$qnT!lv8t
z)ZW<&q5M51_l?Im9Jar2X!jNev;F1JUR)Z?w&xaC+viq$7rKx3x}n{@yts0CAynD<
z&dPk1=`8eS>aIaQwEMFc`e|Hf4`we7;?SjdOUb3_<xaQTTbzqyJA+P4rVrch3<mw)
zxz)k!N@&k4EiB9~#_ at 5HLFZhI^DBdX-Kt|4yVM>JbJYYFs{8rX#hEbHZBL}G$<%r*
z-HxW)u`s<d==29+`t%zwoqF+wXY#xMmypg$`t8h<e3=_1M$s)-eXee#?uyMj<FC}O
z<wl7IZw#$kyBg2wyu`1+QU7hOFR|38bDP#K`ziUcnEPXWeW|SfV{VjKpT`@=rPRl=
z>T1V(n!D6*oU44k*6Lx^nA9xw<#ea>n1+`6wNjU3)2sRXbgbRKss387E3vE>hg4U2
zF7bt!O>@@&u4AKYEXVncL{+}A&-y8Zmt!N<=Ve0}&4oFZ>B{)BZh3w!Hd3zC50|<e
zf7w??*0K5iGcmno{qo<X9GmB*S>LPIUf#M&2)lCq$wo)B{_VW}cw^jDu20`)^Hu6g
zd_Q)UZ at +om>$!e34@{2foEN`xem{!2Vz;^e(nKx)`Q~J7mvu|}<Jh=a{e6>l{Ztv4
HW3&Emjt;!3
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
new file mode 100644
index 0000000000000000000000000000000000000000..08ba4f884605001094c28ce355201e6842b8d08f
GIT binary patch
literal 1058216
zcmeI%L2Fz^902fX)6~S)u(gyH5!u!hJ=CR1#RL&dv8kxF;Gv}+ByN*Uv)F9nW>Zox
z20`%Hn+Gp`0>6bHMeI=#MW`BQ_RXZ}vjy=YEx&<%|9StJ|IC};z63%(pTBf*|Gs^p
zw2|;j7~VCi%v>IL`Baq{jrVh5HjKyXL^vD{#`^=qTs3j73URb*zvrb(9LxEU7*pNs
z{wh(AWnPKp2~$jUk7`HK!m*VY@;OpndiHW(kME|j*h(zpsV<!{G}9%v=J2{3C-TG+
zOI<ovdd at rfeD%1UmnpHF^MfA-OT+#0_`eNluk at MA`_<!#yike7FmkP@{zNlF<#{Ds
z&7BgHM`|~hS{rMvso|dK*%SNQm#>72;g5TFzdLg(&3RZ$_2u*2LngeCbH(G{&dyp&
z#hPKN*j&r!Je22`a}B at am}}(s;ORVGp8MCos`b`$eI6DF5FkK+009C72oNCf#0wlh
z7Q)fd`H<qL$HqI~#Qu2a$myBWjd1w;bRC-??|j)gIC5lkbaW;(!;6#OhOZlq at Z<K!
zf6h$CzZ$=qIoSxO=AU>f2P8m%009C72oNAZfB*pkkF`Mg-{@m~2oFzy009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF{O<z$;}d+bef~-e{qDx%
zt+4OC*d6WPdhONj^!n7o>h${Ag?8#KPp?leETzk0%6-;d+~`-G<xX$06KBWdVtZ;B
zuE!8Ab$g$5`mZ-HUAoYmnr%(BW*>dreZ!%rLTEfV=iu;mEF5S)n13ec4>unycsA!l
zZT|6`AFItj^@w#|8s>lA8HPQVbE&_7G~7vWd)k at UZ-jq7e`s}kgHC at vw0diUPU}W*
zvvqy5dvocP?owzi-R^DNUJb+SN_%5vm}#$e7ptK`KePs&twFqN589zM{DNBT!Jyy0
zzB%Y at gx2EP>T0JKC&Xn2?dvhFYz+EUuZm%Et93RE+Wi}yL0I1GEr!XZ)>K$-_ZM<9
zPMA)~b75g4rUqf*!iSg7zyHo#drtS?yXkvPpTaepJ0*_Qmag7|`^oXxjjFr#bGg36
z6ZfYMdk1Rw&&T^i at l*D{mOCYu`t+Wqz032I{AA4iwzIQV>eq9p#I$~DBURX~&$po!
zJ8A7wU*4M%xAVm6J-@$yd8=pQcv`#EH}Xa$*1hWYZ^qh`E9>w6eB}+^jbnRT*{9^@
zV<**@^Mz&}$#G(L!75+hKm9g|wd=WRH%#Q8!>hZQs#CB3D5g{HY;E3Bu0LAKm--Ty
z<9Pi{sbnkH|CH;~@00Yd)xZB<%<Y~%&rM<FWCggrCzrZq-;&;norl%m&Gm1Ti8<Em
F{|4RFq2d4l
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..17351748513d9
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "RISCV" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
new file mode 100644
index 0000000000000..ec32e53fce0ca
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
@@ -0,0 +1,111 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+
+# CHECK: 0000000000001000 <_start>:
+# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 1004: 00450513 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 1008: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 100c: 1571 addi a0, a0, -0x4 <target>
+# CHECK-NEXT: 100e: 6509 lui a0, 0x2
+# CHECK-NEXT: 1010: 0045059b addiw a1, a0, 0x4 <target>
+# CHECK-NEXT: 1014: 6509 lui a0, 0x2
+# CHECK-NEXT: 1016: 2511 addiw a0, a0, 0x4 <target>
+# CHECK-NEXT: 1018: 00102537 lui a0, 0x102
+# CHECK-NEXT: 101c: c50c sw a1, 0x8(a0) <far_target>
+# CHECK-NEXT: 101e: 00102537 lui a0, 0x102
+# CHECK-NEXT: 1022: 4508 lw a0, 0x8(a0) <far_target>
+# CHECK-NEXT: 1024: 6509 lui a0, 0x2
+# CHECK-NEXT: 1026: 6585 lui a1, 0x1
+# CHECK-NEXT: 1028: 0306 slli t1, t1, 0x1
+# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
+# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
+# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
+# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
+# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
+# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
+# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
+# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
+# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
+
+.global _start
+.text
+
+# The core of the feature being added was address resolution for instruction
+# sequences where a register is populated by immediate values via two
+# separate instructions. First by an instruction that provides the upper bits
+# (auipc, lui ...) followed by another instruction for the lower bits (addi,
+# jalr, ld ...).
+
+
+_start:
+ # Test block 1-3 each focus on a certain starting instruction in a sequences,
+ # the ones that provide the upper bits. The other sequence is another
+ # instruction the provides the lower bits. The second instruction is
+ # arbitrarily chosen to increase code coverage
+
+ # test block #1
+ lla a0, target # addi
+ auipc a0, 0x1
+ c.addi a0, -0x4 # c.addi
+
+ # test block #2
+ c.lui a0, 0x2
+ addiw a1, a0, 0x4 # addiw
+ c.lui a0, 0x2
+ c.addiw a0, 0x4 # c.addiw
+
+ # test block #3
+ lui a0, 0x102
+ sw a1, 0x8(a0) # sw
+ lui a0, 0x102
+ c.lw a0, 0x8(a0) # lw
+
+ # Test block 4 tests instruction interleaving, essentially the code's
+ # ability to keep track of a valid sequence even if multiple other unrelated
+ # instructions separate the two
+
+ # test #4
+ lui a0, 0x2
+ lui a1, 0x1 # unrelated instruction
+ slli t1, t1, 0x1 # unrelated instruction
+ addi a0, a0, 0x4
+ addi a0, a0, 0x1
+
+ # Test 5 ensures that an instruction writing into the zero register does
+ # not trigger resolution because that register's value cannot change and
+ # the sequence is equivalent to never running the first instruction
+
+ # test #5
+ lui x0, 0x200
+ sw a0, 0x8(x0)
+
+ # Test 6 ensures that the newly added functionality is compatible with
+ # code that already worked for branch instructions
+
+ # test #6
+ call func
+
+ # test #7 zcb extension
+ lui x8, 0x102
+ # the immediate value for Zcb extension is heavily bounded, so we will relax
+ # the requirement of hitting one of the labels and focus on correctness of the
+ # resolution. This can be verified by looking at the source: The upper bits of
+ # lui make the far jump related to .skip 0x100000 and then 8 more bytes must be
+ # traversed before we hit far_target--.skip 0x4 and .word 1 in target. Adding 8
+ # to address resolved for the instruction below yields exactly the desired label.
+ c.sb x8, 0(x8)
+
+ # test #8 stack based load/stores
+ lui sp, 0x102
+ c.lwsp a0, 0x8(sp)
+
+# these are the labels that the instructions above are expecteed to resolve to
+.section .data
+.skip 0x4
+target:
+ .word 1
+.skip 0x100000
+far_target:
+ .word 2
+func:
+ ret
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
new file mode 100644
index 0000000000000..49225519a62df
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
@@ -0,0 +1,57 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
+
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0) <ldata+0xfa4>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lw a0, {{-?0x[0-9a-fA-F]+}}(a0) <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <ldata>
+# CHECK: auipc ra, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jalr {{-?0x[0-9a-fA-F]+}}(ra) <func>
+# CHECK: auipc t1, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jr {{-?0x[0-9a-fA-F]+}}(t1) <func>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x12242678>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x1438ad>
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <_start+0xfefff>
+
+.global _start
+.text
+_start:
+ la a0, gdata
+ lla a0, gdata
+ lla a0, gdata
+ lw a0, gdata
+ lla a0, ldata
+
+ call func
+ tail func
+
+ li a0, 0x12345678
+ li a0, 0x1234567890abcdef
+ li a0, 0x10000
+ li a0, 0xfffff
+
+ .skip 0x100000
+func:
+ ret
+
+ldata:
+ .int 0
+
+.data
+gdata:
+ .int 0
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 5ecb33375943f..b5d316e1e3857 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1520,8 +1520,8 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
if (MIA) {
if (Disassembled) {
uint64_t Target;
- bool TargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
- if (TargetKnown && (Target >= Start && Target < End) &&
+ bool BranchTargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
+ if (BranchTargetKnown && (Target >= Start && Target < End) &&
!Targets.count(Target)) {
// On PowerPC and AIX, a function call is encoded as a branch to 0.
// On other PowerPC platforms (ELF), a function call is encoded as
@@ -2356,8 +2356,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
- Inst, SectionAddr + Index, Size, Target);
-
+ Inst, SectionAddr + Index, Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(
+ Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2430,7 +2431,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
break;
}
- // Branch targets are printed just after the instructions.
+ // Branch and instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
bool BBAddrMapLabelAvailable = BBAddrMapLabels.count(Target);
bool LabelAvailable = AllLabels.count(Target);
>From 49f276ea9b2e93e36b298a4130bf7d9a9f4f8f76 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Thu, 12 Jun 2025 16:15:11 -0400
Subject: [PATCH 02/13] Update test output to match previous functionality
As a result of the force push, the context of the old commit history was erased. In the previous iteration changes were made to llvm-objdump which affected non-riscv targets. It was decided to move these changes to another PR. This commit continues the reversion of that iteration
---
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
index 49225519a62df..72e5f586b721e 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
@@ -1,7 +1,7 @@
# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0) <ldata+0xfa4>
+# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0)
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
>From 5e1cf1263e09f453146b75c333e3ffa2dbcc5710 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Tue, 17 Jun 2025 19:36:47 -0400
Subject: [PATCH 03/13] Add support for zclsd and zilsd extensions + tests
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 8 ++++-
.../RISCV/Inputs/riscv32-ar-coverage | Bin 0 -> 9140 bytes
...{riscv-ar-coverage => riscv64-ar-coverage} | Bin 1058216 -> 1058272 bytes
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 30 ++++++++++++++++
...cv-ar-coverage.s => riscv64-ar-coverage.s} | 33 ++++++++----------
5 files changed, 51 insertions(+), 20 deletions(-)
create mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
rename llvm/test/tools/llvm-objdump/RISCV/Inputs/{riscv-ar-coverage => riscv64-ar-coverage} (99%)
mode change 100644 => 100755
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
rename llvm/test/tools/llvm-objdump/RISCV/{riscv-ar-coverage.s => riscv64-ar-coverage.s} (76%)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index e52f5e50832c7..1ffdca4125fab 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -308,7 +308,13 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::C_FLWSP:
case RISCV::C_FSWSP:
case RISCV::C_FLDSP:
- case RISCV::C_FSDSP: {
+ case RISCV::C_FSDSP:
+ case RISCV::C_LD_RV32:
+ case RISCV::C_SD_RV32:
+ case RISCV::C_SDSP_RV32:
+ case RISCV::LD_RV32:
+ case RISCV::C_LDSP_RV32:
+ case RISCV::SD_RV32: {
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
if (TargetRegState && Reg != RISCV::X0) {
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
new file mode 100755
index 0000000000000000000000000000000000000000..8ac5ea52258a1d08b5b96843c64cc9fc52c4db54
GIT binary patch
literal 9140
zcmeHNO=}ZT6uoJUt+q=2sv;sOR&e9c#EL}(TWl?2EC`Bpl}=}-&0uB{W+pW)g05V-
z@=v(&C)A}s#UCJ|8^L(an|UF&8 at qFHFFkY5{d#$GvMRZ6R_YH+rIJ`1mG5GrDUo?3
zKh21g;pe3y<8nhz$%Gs?ab9PS8NkpnP+}CAM{F^Um|zX*{Cs$8pOGY37kn;z=nsPT
zU~UBNHJU6I5fk?FpMK4Jgoljxrm^oH<}EHEChR=!-;oLuh4tVG)_J#<@1$*~YGS?@
z-*<KGxqLX&|G2tPdW`Td<BY}Sp~_Wo&j0H7+o+H8e$PNA;Q9J|-+ja<;W_`~cfakE
zsHp;~fGVI0r~;~hDxeCe0;+&2pbDr0M^xY<{>fY~^EnmrdF}R>Bc7n`s(>n>3aA3A
zfGVI0r~;~hDxeCe0;+&2 at V_gt^a?jj!qnT5QUqE~c5c<eTBq8GYMr@;OSV<()EYh?
zd!d&m%<qL;LF@%+ByXjDl_ZL~Ekj&4YUiYtq at H1(o4dSM>S6pcNbXkZ_2o)+!Kpe6
zhm|rvb at PXCV`Jv`_VYvW81mCY@#zEc*?h2ge(PTW<IaGwk+NJMDdwjHr#WGq1xZJo
zxSa*gcHDI~yJ5?}8T#V*yK%Z3iODwIv}rPK6nc3nOT@{7UM7wa({Zyb2{*f0kc#8A
zqbP_`!U37P3Exb!Bxkvo*`Cb$lDWxtkVyg{YNUuWX)Ld=Ej at YkAiws%Jo$<Q_augQ
zFzl?A-~<xXkbT3u5Vnu|4m9e<odouAKY^fZ+*jaP>|;C&{KPH;`?#k-aIb><5j1<A
z1I}6Y@%tbaiyYiwui_3kXW6%p9s+*@v;00X<YvEv7XhXRUHLr26#(aT2Bk{A*I{FO
z-U}qi=ZZqFB66<abgU5 at 0Pkk)eMRIgf=Ph7T3wppRs&F(oDtb0DU4^)5 at 5LR9r~`D
JO8&5Ye*m?Pl-~dV
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
old mode 100644
new mode 100755
similarity index 99%
rename from llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
rename to llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
index 08ba4f884605001094c28ce355201e6842b8d08f..ceaf049b9a4fef2f01a311a6b5351dd31b5c931a
GIT binary patch
delta 487
zcmZ9Jze_?<6vyv<srfYXh=@u<$H$YDf^2JuRIoYx3-tNS2(-i>p)UOzYzYj98x2w|
zIR*|c4LJ+_3q^C#+St+e3hBV-e$V|LF86!6{c+-boajV&_B#3|r<hTxfrq=f+%&h%
zZd6*aUp+oFcb{9!-FqGwl%-df&6Q`D%Fe)pFK*F6u!)`mjsfE5%=QAYjmQa!m?JEN
zm9P=>gq at HH2jL_Z2p6$9M09_Dc_m75ewu8MR1T{8G2 at 3~31MrkRH_#@%CSsK(@IB1
zQ>;|=X{T$3<P6D+EJCdN#I2K{fuLpjGCQ;2wE0_{VuavVz#OxGWACpY6CViMJS;*X
z at CVl?wq#|UNz|E&h;#^URaVm~`+GH3s2}P~&9j!CV+E~}F>SR$rtm6|?v^F{u&lrh
z=P4npaKfA748bRQDk!`yMk>U8cW9>L#!W5~hwz1AmG?z53~@PP=HE0A)2I9Z0ugHV
delta 387
zcmaEG+F`|MhY1>t8WT0|b9ymAfY)Y0Mt(-lFeo={vL=%{ha1D6-!InbC{13-D6zSK
z=^QVQxrzV-Lx;Jd0E3e2W<iBr{7nXJ28?Y6Ol=0tZ3ZlD2CQucY;6YYZ3Y}|2ApjM
zTx|y2Z3aAT2E1(seA^88IX-L_F!;kiJwQc(g}<r6F%)QDQD$*+83UvDbZG?v8_wiJ
z!vcf&s^p~U%?bhrlML9V?^6&EVq}|sQ9(dlk{9eg4h9|tpgWL&&~!#c0rBYuiUJ0V
z>eCZ}Y)NB~G!rYs1STYPK&H<0iHZWVH1rG at N)n6GQ%e}qO7oH#R8sT|8PXDq;-P{n
z6?#S>LF4KEN&<nCH!!knU!WwgfRWK_x}%CfJ!9DPgDL{%j49K9stDMNRzRKe0csV<
enVi#oRRy#eGp1Ln3fObL00tQd*i8PYFAo6TL0BCC
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
new file mode 100644
index 0000000000000..2e1a109f9ec86
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -0,0 +1,30 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv32-ar-coverage | FileCheck %s
+
+# CHECK: 00001000 <_start>:
+# CHECK-NEXT: 1000: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 1004: 0559 addi a0, a0, 0x16 <target>
+# CHECK-NEXT: 1006: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 100a: 6910 ld a2, 0x10(a0) <target>
+# CHECK-NEXT: 100c: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 1010: 00c53523 sd a2, 0xa(a0) <target>
+# CHECK-NEXT: 1014: 0000 unimp
+
+# the structure of this test file is similar to that of riscv64-ar-coverage
+# with the major difference being that these tests are focused on instructions
+# for 32 bit architecture
+
+.global _start
+.text
+_start:
+ auipc a0, 0x0
+ addi a0, a0, 0x16 # addi -- behavior changes with differentr architectures
+
+ auipc a0, 0x0
+ c.ld a2, 0x10(a0) # zclsd instruction
+
+ auipc a0, 0x0
+ sd a2, 0xa(a0) # zilsd instruction
+
+.skip 0x2
+target:
+ ret:
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
similarity index 76%
rename from llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
rename to llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index ec32e53fce0ca..003defd351dfd 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+# RUN: llvm-objdump -d %p/Inputs/riscv64-ar-coverage | FileCheck %s
# CHECK: 0000000000001000 <_start>:
# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
@@ -22,23 +22,22 @@
# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
-# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
-# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
-# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
-# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
+# CHECK-NEXT: 103e: 640d lui s0, 0x3
+# CHECK-NEXT: 1040: 8800 sb s0, 0x0(s0) <zcb>
+# CHECK-NEXT: 1042: 4522 lw a0, 0x8(sp)
+
.global _start
.text
-# The core of the feature being added was address resolution for instruction
-# sequences where a register is populated by immediate values via two
+# The core of the feature being added was address resolution for instruction
+# sequences where an register is populated by immediate values via two
# separate instructions. First by an instruction that provides the upper bits
# (auipc, lui ...) followed by another instruction for the lower bits (addi,
# jalr, ld ...).
-
_start:
- # Test block 1-3 each focus on a certain starting instruction in a sequences,
+ # Test block 1-3 each focus on a certain starting instruction in a sequences,
# the ones that provide the upper bits. The other sequence is another
# instruction the provides the lower bits. The second instruction is
# arbitrarily chosen to increase code coverage
@@ -69,7 +68,7 @@ _start:
lui a1, 0x1 # unrelated instruction
slli t1, t1, 0x1 # unrelated instruction
addi a0, a0, 0x4
- addi a0, a0, 0x1
+ addi a0, a0, 0x1 # verify register tracking terminates
# Test 5 ensures that an instruction writing into the zero register does
# not trigger resolution because that register's value cannot change and
@@ -86,17 +85,10 @@ _start:
call func
# test #7 zcb extension
- lui x8, 0x102
- # the immediate value for Zcb extension is heavily bounded, so we will relax
- # the requirement of hitting one of the labels and focus on correctness of the
- # resolution. This can be verified by looking at the source: The upper bits of
- # lui make the far jump related to .skip 0x100000 and then 8 more bytes must be
- # traversed before we hit far_target--.skip 0x4 and .word 1 in target. Adding 8
- # to address resolved for the instruction below yields exactly the desired label.
+ lui x8, 0x3
c.sb x8, 0(x8)
# test #8 stack based load/stores
- lui sp, 0x102
c.lwsp a0, 0x8(sp)
# these are the labels that the instructions above are expecteed to resolve to
@@ -104,7 +96,10 @@ _start:
.skip 0x4
target:
.word 1
-.skip 0x100000
+.skip 0xff8
+zcb:
+ .word 1
+.skip 0xff004
far_target:
.word 2
func:
>From 11c50dccff5b68cf28c97eed83df8934dd425c68 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Wed, 18 Jun 2025 00:14:23 -0400
Subject: [PATCH 04/13] Pass subtargetinfo as function argument
Follows up on discussion from linked pull request that has been closed. Essentially, not having a target specific factory method
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 ++-
llvm/lib/MC/MCInstrAnalysis.cpp | 3 ++-
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 22 +++++++------------
llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +-
4 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 1f05e8546c3d1..614f220b283be 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -19,6 +19,7 @@
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Compiler.h"
#include <cstdint>
#include <vector>
@@ -185,7 +186,7 @@ class LLVM_ABI MCInstrAnalysis {
/// Given an instruction that accesses a memory address, try to compute
/// the target address. Return true on success, and the address in \p Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target) const;
+ uint64_t Size, uint64_t &Target, const MCSubtargetInfo &STI) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 1ae0c91a2590c..2dc18682eb0e3 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -32,7 +32,8 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
uint64_t Size,
- uint64_t &Target) const {
+ uint64_t &Target,
+ const MCSubtargetInfo &STI) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 1ffdca4125fab..8912ae5177a94 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -131,7 +131,6 @@ namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
- unsigned int ArchRegWidth;
static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -168,8 +167,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, unsigned int ArchRegWidth)
- : MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
+ : MCInstrAnalysis(Info) {}
void resetState() override { GPRValidMask.reset(); }
@@ -245,7 +244,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo &STI) const override {
+ unsigned int ArchRegWidth = STI.getTargetTriple().getArchPointerBitWidth();
switch(Inst.getOpcode()) {
default:
return false;
@@ -420,12 +420,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
} // end anonymous namespace
-static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info, 32);
-}
-
-static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info, 64);
+static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info);
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
@@ -446,9 +442,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
+ TargetRegistry::RegisterMCInstrAnalysis(*T,
+ createRISCVInstrAnalysis);
}
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(),
- createRISCV32InstrAnalysis);
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(),
- createRISCV64InstrAnalysis);
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index b5d316e1e3857..3612ce9e30c6a 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2358,7 +2358,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
Inst, SectionAddr + Index, Size, Target) ||
DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target);
+ Inst, SectionAddr + Index, Size, Target, *DT->SubtargetInfo);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 22415835e2be5dc5eeca08bfbf440db1548d5708 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Wed, 18 Jun 2025 00:16:37 -0400
Subject: [PATCH 05/13] Run clang format
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 ++-
llvm/lib/MC/MCInstrAnalysis.cpp | 3 +--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 6 +++---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 3 ++-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 614f220b283be..a0411a365791a 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -186,7 +186,8 @@ class LLVM_ABI MCInstrAnalysis {
/// Given an instruction that accesses a memory address, try to compute
/// the target address. Return true on success, and the address in \p Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target, const MCSubtargetInfo &STI) const;
+ uint64_t Size, uint64_t &Target,
+ const MCSubtargetInfo &STI) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 2dc18682eb0e3..d726b1c0eabbe 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -31,8 +31,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
}
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size,
- uint64_t &Target,
+ uint64_t Size, uint64_t &Target,
const MCSubtargetInfo &STI) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 8912ae5177a94..237d1a2d4de5f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -244,7 +244,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, const MCSubtargetInfo &STI) const override {
+ uint64_t &Target,
+ const MCSubtargetInfo &STI) const override {
unsigned int ArchRegWidth = STI.getTargetTriple().getArchPointerBitWidth();
switch(Inst.getOpcode()) {
default:
@@ -442,7 +443,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
- TargetRegistry::RegisterMCInstrAnalysis(*T,
- createRISCVInstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
}
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 3612ce9e30c6a..a51f5a05b0fbb 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2358,7 +2358,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
Inst, SectionAddr + Index, Size, Target) ||
DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target, *DT->SubtargetInfo);
+ Inst, SectionAddr + Index, Size, Target,
+ *DT->SubtargetInfo);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 7635b7004734c44279e4062d9e1086ab2acad39c Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Thu, 19 Jun 2025 14:39:30 -0400
Subject: [PATCH 06/13] Remove precanned binaries from tests and invoke clang
during tests
---
cross-project-tests/lit.cfg.py | 2 +-
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 +
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 3 +-
.../llvm-objdump/RISCV/riscv64-ar-coverage.s | 3 +-
.../tools/llvm-objdump/RISCV/Inputs/riscv-ar | Bin 1062552 -> 0 bytes
.../RISCV/Inputs/riscv32-ar-coverage | Bin 9140 -> 0 bytes
.../RISCV/Inputs/riscv64-ar-coverage | Bin 1058272 -> 0 bytes
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 -
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 57 ------------------
9 files changed, 7 insertions(+), 62 deletions(-)
create mode 100644 cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
rename {llvm/test => cross-project-tests}/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s (87%)
rename {llvm/test => cross-project-tests}/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s (96%)
delete mode 100644 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
delete mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
delete mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
delete mode 100644 llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
delete mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
diff --git a/cross-project-tests/lit.cfg.py b/cross-project-tests/lit.cfg.py
index b35c643ac898c..7b95c09bbcfa0 100644
--- a/cross-project-tests/lit.cfg.py
+++ b/cross-project-tests/lit.cfg.py
@@ -19,7 +19,7 @@
config.test_format = lit.formats.ShTest(not llvm_config.use_lit_shell)
# suffixes: A list of file extensions to treat as test files.
-config.suffixes = [".c", ".cl", ".cpp", ".m"]
+config.suffixes = [".c", ".cl", ".cpp", ".m", ".s"]
# excludes: A list of directories to exclude from the testsuite. The 'Inputs'
# subdirectories contain auxiliary inputs for various tests in their parent
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg b/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..0da1d6fab83ab
--- /dev/null
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if "clang" not in config.available_features or "RISCV" not in config.targets_to_build:
+ config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
similarity index 87%
rename from llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
rename to cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
index 2e1a109f9ec86..c5994ce7fada6 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -1,4 +1,5 @@
-# RUN: llvm-objdump -d %p/Inputs/riscv32-ar-coverage | FileCheck %s
+# RUN: %clang --target=fuchsia-elf-riscv32 -march=rv32g_zclsd_zilsd %s -nostdlib -o %t
+# RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: 00001000 <_start>:
# CHECK-NEXT: 1000: 00000517 auipc a0, 0x0
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
similarity index 96%
rename from llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
rename to cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index 003defd351dfd..e688074f3914f 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -1,4 +1,5 @@
-# RUN: llvm-objdump -d %p/Inputs/riscv64-ar-coverage | FileCheck %s
+# RUN: %clang --target=fuchsia-elf-riscv64 -march=rv64gc_zcb %s -nostdlib -o %t
+# RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: 0000000000001000 <_start>:
# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
deleted file mode 100644
index bc335bc24f88d8577308802b27dbded31834a89f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 1062552
zcmeI$&ubk;902fX)2G!I8Z9-&ibR at v5g$oxZPB7BRz;|aVnI*gH7`vbHa~cIDXk(F
zu?NMo;z98!c*#ZR(W8HWUd4-eRYVbl#+lujG}%-sNWsHr;q7<!JM*2H{p?gQ?>>9x
zxt%+9gmMjq-$L~?TxX_o$Lo`Iq7|Q~!ilga-tP(f!X5E>SCy*=PSqjy*4O;bt#NnG
z55<`3zRdm2SjLrDc9>$S`={%hG;zF24Ea4$UD|tjZpQhXD6#aXy7Z1=G*8rsIlFD%
zjk at tXq7lnGlvvhF991sAM`*;gw3m35SbSdnY0$0e8v85zZtgSfFI}(1y6XMv$6LOq
zwbE}bf4^otm}e at n+FQ)U*IBM=i$@+;!pYnyvF!6gx4p8|o~YJL at 0?hkf9Y)a?z6L>
zp8oUey`{bxQ+ at f}-|URf59VBP{A+!EDWzgfl^V<a*YbBb+!%kP at mwsw%`SU#e{rbJ
zV9c%M`R>mB<voADUa$XSuFu`u!tU~&xAjO6AV7cs0RjXF5FkL{<^m%JhQrXYt6}8G
zaM<6vx?aat6^D*oy*|=P`Db^168{JF=PO?fjSLNkxo~*s_}QcP9%@~kJH9#=4z<4j
z at Tu1R)`1Tu<Nf=u(*5 at zPR$;VweK9e`MR<M2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+0D)T<c<;)sk2R720RjXF5FkK+009C72oSg}0z-M$
z@!{Jty-5iWAV7cs0RjXF5FkK+0D=F9z^NzWKKi|tnTuh^L~OSD7au>`n_QllUYJ}S
zpYEjA`N`$U>2A8sq}*G*nU#KQgfqRxH)s1#jGj4jdUWDMd!l{f-`{CR)xA4}#-AJR
zsPcP4X#5>wZyw(r-db>P&Yx at KM>g_RW8?O~Mt<u&59NGw{)eml_We9k<$qnT!lv8t
z)ZW<&q5M51_l?Im9Jar2X!jNev;F1JUR)Z?w&xaC+viq$7rKx3x}n{@yts0CAynD<
z&dPk1=`8eS>aIaQwEMFc`e|Hf4`we7;?SjdOUb3_<xaQTTbzqyJA+P4rVrch3<mw)
zxz)k!N@&k4EiB9~#_ at 5HLFZhI^DBdX-Kt|4yVM>JbJYYFs{8rX#hEbHZBL}G$<%r*
z-HxW)u`s<d==29+`t%zwoqF+wXY#xMmypg$`t8h<e3=_1M$s)-eXee#?uyMj<FC}O
z<wl7IZw#$kyBg2wyu`1+QU7hOFR|38bDP#K`ziUcnEPXWeW|SfV{VjKpT`@=rPRl=
z>T1V(n!D6*oU44k*6Lx^nA9xw<#ea>n1+`6wNjU3)2sRXbgbRKss387E3vE>hg4U2
zF7bt!O>@@&u4AKYEXVncL{+}A&-y8Zmt!N<=Ve0}&4oFZ>B{)BZh3w!Hd3zC50|<e
zf7w??*0K5iGcmno{qo<X9GmB*S>LPIUf#M&2)lCq$wo)B{_VW}cw^jDu20`)^Hu6g
zd_Q)UZ at +om>$!e34@{2foEN`xem{!2Vz;^e(nKx)`Q~J7mvu|}<Jh=a{e6>l{Ztv4
HW3&Emjt;!3
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
deleted file mode 100755
index 8ac5ea52258a1d08b5b96843c64cc9fc52c4db54..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 9140
zcmeHNO=}ZT6uoJUt+q=2sv;sOR&e9c#EL}(TWl?2EC`Bpl}=}-&0uB{W+pW)g05V-
z@=v(&C)A}s#UCJ|8^L(an|UF&8 at qFHFFkY5{d#$GvMRZ6R_YH+rIJ`1mG5GrDUo?3
zKh21g;pe3y<8nhz$%Gs?ab9PS8NkpnP+}CAM{F^Um|zX*{Cs$8pOGY37kn;z=nsPT
zU~UBNHJU6I5fk?FpMK4Jgoljxrm^oH<}EHEChR=!-;oLuh4tVG)_J#<@1$*~YGS?@
z-*<KGxqLX&|G2tPdW`Td<BY}Sp~_Wo&j0H7+o+H8e$PNA;Q9J|-+ja<;W_`~cfakE
zsHp;~fGVI0r~;~hDxeCe0;+&2pbDr0M^xY<{>fY~^EnmrdF}R>Bc7n`s(>n>3aA3A
zfGVI0r~;~hDxeCe0;+&2 at V_gt^a?jj!qnT5QUqE~c5c<eTBq8GYMr@;OSV<()EYh?
zd!d&m%<qL;LF@%+ByXjDl_ZL~Ekj&4YUiYtq at H1(o4dSM>S6pcNbXkZ_2o)+!Kpe6
zhm|rvb at PXCV`Jv`_VYvW81mCY@#zEc*?h2ge(PTW<IaGwk+NJMDdwjHr#WGq1xZJo
zxSa*gcHDI~yJ5?}8T#V*yK%Z3iODwIv}rPK6nc3nOT@{7UM7wa({Zyb2{*f0kc#8A
zqbP_`!U37P3Exb!Bxkvo*`Cb$lDWxtkVyg{YNUuWX)Ld=Ej at YkAiws%Jo$<Q_augQ
zFzl?A-~<xXkbT3u5Vnu|4m9e<odouAKY^fZ+*jaP>|;C&{KPH;`?#k-aIb><5j1<A
z1I}6Y@%tbaiyYiwui_3kXW6%p9s+*@v;00X<YvEv7XhXRUHLr26#(aT2Bk{A*I{FO
z-U}qi=ZZqFB66<abgU5 at 0Pkk)eMRIgf=Ph7T3wppRs&F(oDtb0DU4^)5 at 5LR9r~`D
JO8&5Ye*m?Pl-~dV
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
deleted file mode 100755
index ceaf049b9a4fef2f01a311a6b5351dd31b5c931a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 1058272
zcmeI%&1;-R7y$6;M{3fKkWxyEh_11PUR;|XHh3|`MiFDhgP;dVH at lm5vDw7kO-Xt&
z2%;CEHxFKl7yTo=`lpCz5k(M<GyBdY&6=VJUczr+-)G)u=9zitx9<i at KVDdT?dXvs
zp|oS+=P<mRsxtF=;MR1N7>oDwVJ=L>>tr|`PQ?4;!(26Sz6x=)YQN>BOB~PnV=<<>
zxuaELG?sZKmM2Ux)jh7AO$*0XV#w!6b?Mp5{b;<A#$qe6jHkME#!yR_*lNS;Zk)^$
zODuKiSm`+*<nxWj?YvBh<(%*QFlY_;%j5qxq`lH-KJPagFXn|xOmkC<T<fVnS<6tv
z?A~Q7cS}qjsoibW`)l=?;hyQ)6Z`8o-wj`U^Yzx--`#&E%{i#0`to`5fC*3MT=DpQ
zXJ;*?V$CpBY~IV~JeB8{a}B at an48M)!O1*cp8J<StM%4%eI6DF5FkK+009C72oNA}
z=mjpE58>R{LP+tW^Aqi_Vt=B2_VTsMQ{nXY={mkJ(f+i3;@H`-v9W8R7M{EGFnl>R
z6 at J{l^~af3_<VZd&?7k at 0RjXF5FkK+009C72oN{~0_Fck55Z9!fdByl1PBlyK!5-N
z0t5&UI6%O^{SQEqB0zuu0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7{uhCxan(<@uW!cC
z>-3xV!jW$5j`i-n^kQdreP(HOcKzy7BlT8h*Jqbn>C#NO`<-ULS9Mm}-DW$^j>*;4
zjk`0c(`c-&Rh_%NeskDsHma~(g;oq<vD5vq-FvyVxOk&BGgqIf&;7$Gj||732w`gf
z#N)%;@o>DhKYuFcPuKPrRCnVcjLbim=ZCBN*SV1M<0I=#=ltmUmxuYEcJ{9l!V4*J
zbSykb at Q<`Bu|F05ey&jObO-I;dZ>5T2JQOo?nZriqjR_Qe5V!at*vf<Yc&kBcN+aW
z!%Snf)2xODy-**tHwW>qF=&MP at C&Xt27_K_d1KJ-hkA2ub+z4%6XG(1#&V2z`h#B8
zt75pc83v8s?e-w7Y;>F9QY+kVE{ByyZz-qagqU3F$J;?zy7B(a>u<gB>LVxnZ{74g
zr%z#;%bgPAH at B}<@5NqfB6g$ZZvA|&FY)5u)M2lBfA*43#cq0c%Kq==PKl-dM4XfM
zF3(f)mtyYMot?E(zn(iKru9=hR)yXAd>iVqlh!Wv<$Wn}J5Nk=QY-tHxBObnrL{}_
zRNkn>QLoYaS7L3-mGyUjZ+U|oaqQ7n_9?lA*h%%}e4&;{a-7^<u*#3_|7J|b+Vxzu
z8z%GbZ)-PGbw=wyi0PCY`5A}La((qX-&>^Am$(v#M$eRHKg{*xdE%LvI~hO4zkL7c
lujuaCW52X-pREA5OCrazZ%J>)&O!B8rmOn7GVw9>e*r8Lt>XXy
diff --git a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
deleted file mode 100644
index 17351748513d9..0000000000000
--- a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not "RISCV" in config.root.targets:
- config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
deleted file mode 100644
index 72e5f586b721e..0000000000000
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
+++ /dev/null
@@ -1,57 +0,0 @@
-# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
-
-# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0)
-# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
-# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
-# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: lw a0, {{-?0x[0-9a-fA-F]+}}(a0) <gdata>
-# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <ldata>
-# CHECK: auipc ra, {{-?0x[0-9a-fA-F]+}}
-# CHECK: jalr {{-?0x[0-9a-fA-F]+}}(ra) <func>
-# CHECK: auipc t1, {{-?0x[0-9a-fA-F]+}}
-# CHECK: jr {{-?0x[0-9a-fA-F]+}}(t1) <func>
-# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x12242678>
-# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x1438ad>
-# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <_start+0xfefff>
-
-.global _start
-.text
-_start:
- la a0, gdata
- lla a0, gdata
- lla a0, gdata
- lw a0, gdata
- lla a0, ldata
-
- call func
- tail func
-
- li a0, 0x12345678
- li a0, 0x1234567890abcdef
- li a0, 0x10000
- li a0, 0xfffff
-
- .skip 0x100000
-func:
- ret
-
-ldata:
- .int 0
-
-.data
-gdata:
- .int 0
>From 9dff558f2196102098b7b545719f0755035c9d35 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Fri, 20 Jun 2025 19:29:16 -0400
Subject: [PATCH 07/13] Fix typo
---
.../tools/llvm-objdump/RISCV/riscv32-ar-coverage.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
index c5994ce7fada6..0c5167f83b71d 100644
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -18,7 +18,7 @@
.text
_start:
auipc a0, 0x0
- addi a0, a0, 0x16 # addi -- behavior changes with differentr architectures
+ addi a0, a0, 0x16 # addi -- behavior changes with different architectures
auipc a0, 0x0
c.ld a2, 0x10(a0) # zclsd instruction
>From b738bf1ea48fea576d7b9821b34894054ee399ce Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Fri, 20 Jun 2025 19:36:20 -0400
Subject: [PATCH 08/13] Enable address resolution for load/store instructions
relative to zero register
Handles the case of users writing instructions that access a data in the first page of a program. Such an instruction would not need the upper bits so a user is likely to use the zero register as the base to add the immediate to
---
.../tools/llvm-objdump/RISCV/riscv64-ar-coverage.s | 11 +++++++----
.../Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 2 +-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index e688074f3914f..2b52d64d30160 100644
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -1,4 +1,5 @@
# RUN: %clang --target=fuchsia-elf-riscv64 -march=rv64gc_zcb %s -nostdlib -o %t
+# RUN: llvm-objcopy --add-symbol abs=0,global %t
# RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: 0000000000001000 <_start>:
@@ -20,7 +21,7 @@
# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
-# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
+# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero) <abs+0x8>
# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
# CHECK-NEXT: 103e: 640d lui s0, 0x3
@@ -71,9 +72,11 @@ _start:
addi a0, a0, 0x4
addi a0, a0, 0x1 # verify register tracking terminates
- # Test 5 ensures that an instruction writing into the zero register does
- # not trigger resolution because that register's value cannot change and
- # the sequence is equivalent to never running the first instruction
+ # Test 5 check instructions providing upper bits does not change the tracked
+ # value of zero register + ensure load/store instructions accessing data
+ # relative to the zero register trigger address resolution. The latter kind
+ # of instructions are essentially memory accesses relative to the zero
+ # register
# test #5
lui x0, 0x200
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 237d1a2d4de5f..2a8572cb7b414 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -318,7 +318,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::SD_RV32: {
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
- if (TargetRegState && Reg != RISCV::X0) {
+ if (TargetRegState) {
Target = *TargetRegState + Inst.getOperand(2).getImm();
return true;
}
>From 936182842c1cd234ab1597a27ca7aedd233bbb93 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Mon, 23 Jun 2025 16:58:11 -0400
Subject: [PATCH 09/13] Edit comments to follow LLVM coding style
---
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 11 +--
.../llvm-objdump/RISCV/riscv64-ar-coverage.s | 67 +++++++++----------
2 files changed, 36 insertions(+), 42 deletions(-)
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
index 0c5167f83b71d..75b6e63a6d2e8 100644
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -10,21 +10,22 @@
# CHECK-NEXT: 1010: 00c53523 sd a2, 0xa(a0) <target>
# CHECK-NEXT: 1014: 0000 unimp
-# the structure of this test file is similar to that of riscv64-ar-coverage
+# The structure of this test file is similar to that of riscv64-ar-coverage
# with the major difference being that these tests are focused on instructions
-# for 32 bit architecture
+# for 32 bit architecture.
.global _start
.text
_start:
auipc a0, 0x0
- addi a0, a0, 0x16 # addi -- behavior changes with different architectures
+ addi a0, a0, 0x16 # addi -- behavior changes with different architectures.
+ # Test Zclsd and Zilsd instructions respectively
auipc a0, 0x0
- c.ld a2, 0x10(a0) # zclsd instruction
+ c.ld a2, 0x10(a0)
auipc a0, 0x0
- sd a2, 0xa(a0) # zilsd instruction
+ sd a2, 0xa(a0)
.skip 0x2
target:
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index 2b52d64d30160..50518493be3ae 100644
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
+++ b/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -28,74 +28,67 @@
# CHECK-NEXT: 1040: 8800 sb s0, 0x0(s0) <zcb>
# CHECK-NEXT: 1042: 4522 lw a0, 0x8(sp)
+# The core of the feature being added was address resolution for instruction
+# sequences where a register is populated by immediate values via two
+# separate instructions. First by an instruction that provides the upper bits
+# (auipc, lui, etc) followed by another instruction for the lower bits (addi,
+# jalr, ld, etc.).
.global _start
.text
-# The core of the feature being added was address resolution for instruction
-# sequences where an register is populated by immediate values via two
-# separate instructions. First by an instruction that provides the upper bits
-# (auipc, lui ...) followed by another instruction for the lower bits (addi,
-# jalr, ld ...).
-
_start:
- # Test block 1-3 each focus on a certain starting instruction in a sequences,
- # the ones that provide the upper bits. The other sequence is another
- # instruction the provides the lower bits. The second instruction is
- # arbitrarily chosen to increase code coverage
+ # Test block 1-3 each focus on a certain starting instruction in a sequence.
+ # Starting instructions are the ones that provide the upper bits. The other
+ # instruction in the sequence is the one that provides the lower bits. The
+ # second instruction is arbitrarily chosen to increase code coverage.
- # test block #1
- lla a0, target # addi
+ # Test block #1.
+ lla a0, target
auipc a0, 0x1
- c.addi a0, -0x4 # c.addi
+ c.addi a0, -0x4
- # test block #2
+ # Test block #2.
c.lui a0, 0x2
- addiw a1, a0, 0x4 # addiw
+ addiw a1, a0, 0x4
c.lui a0, 0x2
- c.addiw a0, 0x4 # c.addiw
+ c.addiw a0, 0x4
- # test block #3
+ # Test block #3.
lui a0, 0x102
- sw a1, 0x8(a0) # sw
+ sw a1, 0x8(a0)
lui a0, 0x102
- c.lw a0, 0x8(a0) # lw
+ c.lw a0, 0x8(a0)
- # Test block 4 tests instruction interleaving, essentially the code's
+ # Test block 4 tests instruction interleaving. Essentially the code's
# ability to keep track of a valid sequence even if multiple other unrelated
- # instructions separate the two
-
- # test #4
+ # instructions separate the two.
lui a0, 0x2
- lui a1, 0x1 # unrelated instruction
- slli t1, t1, 0x1 # unrelated instruction
+ lui a1, 0x1 # Unrelated instruction.
+ slli t1, t1, 0x1 # Unrelated instruction.
addi a0, a0, 0x4
- addi a0, a0, 0x1 # verify register tracking terminates
+ addi a0, a0, 0x1 # Verify register tracking terminates.
- # Test 5 check instructions providing upper bits does not change the tracked
- # value of zero register + ensure load/store instructions accessing data
+ # Test 5 checks instructions providing upper bits do not change the tracked
+ # value of zero register. Also ensures load/store instructions accessing data
# relative to the zero register trigger address resolution. The latter kind
# of instructions are essentially memory accesses relative to the zero
- # register
-
- # test #5
+ # register.
lui x0, 0x200
sw a0, 0x8(x0)
# Test 6 ensures that the newly added functionality is compatible with
- # code that already worked for branch instructions
-
- # test #6
+ # code that already worked for branch instructions.
call func
- # test #7 zcb extension
+ # Test #7 -- zcb extension.
lui x8, 0x3
c.sb x8, 0(x8)
- # test #8 stack based load/stores
+ # Test #8 -- stack based load/stores.
c.lwsp a0, 0x8(sp)
-# these are the labels that the instructions above are expecteed to resolve to
+# These are the labels that the instructions above are expected to resolve to.
.section .data
.skip 0x4
target:
>From e942f6326512b61703123ebcb1f985330edeafe8 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Mon, 23 Jun 2025 20:11:46 -0400
Subject: [PATCH 10/13] Use llvm-mc over clang for compilation in tests
---
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 -
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 32 ---------
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 +
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 32 +++++++++
.../llvm-objdump/RISCV/riscv64-ar-coverage.s | 72 +++++++++----------
5 files changed, 68 insertions(+), 72 deletions(-)
delete mode 100644 cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
delete mode 100644 cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
rename {cross-project-tests => llvm/test}/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s (53%)
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg b/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
deleted file mode 100644
index 0da1d6fab83ab..0000000000000
--- a/cross-project-tests/tools/llvm-objdump/RISCV/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if "clang" not in config.available_features or "RISCV" not in config.targets_to_build:
- config.unsupported = True
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
deleted file mode 100644
index 75b6e63a6d2e8..0000000000000
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
+++ /dev/null
@@ -1,32 +0,0 @@
-# RUN: %clang --target=fuchsia-elf-riscv32 -march=rv32g_zclsd_zilsd %s -nostdlib -o %t
-# RUN: llvm-objdump -d %t | FileCheck %s
-
-# CHECK: 00001000 <_start>:
-# CHECK-NEXT: 1000: 00000517 auipc a0, 0x0
-# CHECK-NEXT: 1004: 0559 addi a0, a0, 0x16 <target>
-# CHECK-NEXT: 1006: 00000517 auipc a0, 0x0
-# CHECK-NEXT: 100a: 6910 ld a2, 0x10(a0) <target>
-# CHECK-NEXT: 100c: 00000517 auipc a0, 0x0
-# CHECK-NEXT: 1010: 00c53523 sd a2, 0xa(a0) <target>
-# CHECK-NEXT: 1014: 0000 unimp
-
-# The structure of this test file is similar to that of riscv64-ar-coverage
-# with the major difference being that these tests are focused on instructions
-# for 32 bit architecture.
-
-.global _start
-.text
-_start:
- auipc a0, 0x0
- addi a0, a0, 0x16 # addi -- behavior changes with different architectures.
-
- # Test Zclsd and Zilsd instructions respectively
- auipc a0, 0x0
- c.ld a2, 0x10(a0)
-
- auipc a0, 0x0
- sd a2, 0xa(a0)
-
-.skip 0x2
-target:
- ret:
diff --git a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..9dd5a0eedea08
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if "RISCV" not in config.targets_to_build:
+ config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
new file mode 100644
index 0000000000000..2aa617bf3e8b4
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -0,0 +1,32 @@
+# RUN: llvm-mc -riscv-add-build-attributes -triple=riscv32 -filetype=obj -mattr=+zclsd,+zilsd %s -o %t
+# RUN: llvm-objdump -d %t | FileCheck %s
+
+# CHECK: 00000000 <_start>:
+# CHECK-NEXT 0: 00000517 auipc a0, 0x0
+# CHECK-NEXT 4: 0559 addi a0, a0, 0x16 <target>
+# CHECK-NEXT 6: 00000517 auipc a0, 0x0
+# CHECK-NEXT a: 6910 ld a2, 0x10(a0) <target>
+# CHECK-NEXT c: 00000517 auipc a0, 0x0
+# CHECK-NEXT 10: 00c53523 sd a2, 0xa(a0) <target>
+# CHECK-NEXT 14: 0000 unimp
+
+# The structure of this test file is similar to that of riscv64-ar-coverage
+# with the major difference being that these tests are focused on instructions
+# for 32 bit architecture.
+
+.global _start
+.text
+_start:
+ auipc a0, 0x0
+ addi a0, a0, 0x16 # addi -- behavior changes with different architectures.
+
+ # Test Zclsd and Zilsd instructions respectively
+ auipc a0, 0x0
+ c.ld a2, 0x10(a0)
+
+ auipc a0, 0x0
+ sd a2, 0xa(a0)
+
+.skip 0x2
+target:
+ ret:
diff --git a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
similarity index 53%
rename from cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
rename to llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index 50518493be3ae..7c129bd7b8a0b 100644
--- a/cross-project-tests/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -1,32 +1,30 @@
-# RUN: %clang --target=fuchsia-elf-riscv64 -march=rv64gc_zcb %s -nostdlib -o %t
-# RUN: llvm-objcopy --add-symbol abs=0,global %t
+# RUN: llvm-mc -riscv-add-build-attributes -triple=riscv64 -filetype=obj -mattr=+f,+c,+zcb %s -o %t
# RUN: llvm-objdump -d %t | FileCheck %s
-# CHECK: 0000000000001000 <_start>:
-# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
-# CHECK-NEXT: 1004: 00450513 addi a0, a0, 0x4 <target>
-# CHECK-NEXT: 1008: 00001517 auipc a0, 0x1
-# CHECK-NEXT: 100c: 1571 addi a0, a0, -0x4 <target>
-# CHECK-NEXT: 100e: 6509 lui a0, 0x2
-# CHECK-NEXT: 1010: 0045059b addiw a1, a0, 0x4 <target>
-# CHECK-NEXT: 1014: 6509 lui a0, 0x2
-# CHECK-NEXT: 1016: 2511 addiw a0, a0, 0x4 <target>
-# CHECK-NEXT: 1018: 00102537 lui a0, 0x102
-# CHECK-NEXT: 101c: c50c sw a1, 0x8(a0) <far_target>
-# CHECK-NEXT: 101e: 00102537 lui a0, 0x102
-# CHECK-NEXT: 1022: 4508 lw a0, 0x8(a0) <far_target>
-# CHECK-NEXT: 1024: 6509 lui a0, 0x2
-# CHECK-NEXT: 1026: 6585 lui a1, 0x1
-# CHECK-NEXT: 1028: 0306 slli t1, t1, 0x1
-# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
-# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
-# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
-# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero) <abs+0x8>
-# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
-# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
-# CHECK-NEXT: 103e: 640d lui s0, 0x3
-# CHECK-NEXT: 1040: 8800 sb s0, 0x0(s0) <zcb>
-# CHECK-NEXT: 1042: 4522 lw a0, 0x8(sp)
+# CHECK: 0000000000000000 <_start>:
+# CHECK-NEXT: 0: 00010517 auipc a0, 0x10
+# CHECK-NEXT: 4: 00450513 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 8: 00010517 auipc a0, 0x10
+# CHECK-NEXT: c: 1571 addi a0, a0, -0x4 <target>
+# CHECK-NEXT: e: 6541 lui a0, 0x10
+# CHECK-NEXT: 10: 0045059b addiw a1, a0, 0x4 <target>
+# CHECK-NEXT: 14: 6541 lui a0, 0x10
+# CHECK-NEXT: 16: 2511 addiw a0, a0, 0x4 <target>
+# CHECK-NEXT: 18: 00110537 lui a0, 0x110
+# CHECK-NEXT: 1c: c50c sw a1, 0x8(a0) <far_target>
+# CHECK-NEXT: 1e: 00110537 lui a0, 0x110
+# CHECK-NEXT: 22: 4508 lw a0, 0x8(a0) <far_target>
+# CHECK-NEXT: 24: 6541 lui a0, 0x10
+# CHECK-NEXT: 26: 6585 lui a1, 0x1
+# CHECK-NEXT: 28: 0306 slli t1, t1, 0x1
+# CHECK-NEXT: 2a: 0511 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 2c: 0505 addi a0, a0, 0x1
+# CHECK-NEXT: 2e: 00002427 fsw ft0, 0x8(zero) <_start+0x8>
+# CHECK-NEXT: 32: 00110097 auipc ra, 0x110
+# CHECK-NEXT: 36: fda080e7 jalr -0x26(ra) <func>
+# CHECK-NEXT: 3a: 6445 lui s0, 0x11
+# CHECK-NEXT: 3c: 8800 sb s0, 0x0(s0) <zcb>
+# CHECK-NEXT: 3e: 4522 lw a0, 0x8(sp)
# The core of the feature being added was address resolution for instruction
# sequences where a register is populated by immediate values via two
@@ -45,25 +43,25 @@ _start:
# Test block #1.
lla a0, target
- auipc a0, 0x1
+ auipc a0, 0x10
c.addi a0, -0x4
# Test block #2.
- c.lui a0, 0x2
+ c.lui a0, 0x10
addiw a1, a0, 0x4
- c.lui a0, 0x2
+ c.lui a0, 0x10
c.addiw a0, 0x4
# Test block #3.
- lui a0, 0x102
+ lui a0, 0x110
sw a1, 0x8(a0)
- lui a0, 0x102
+ lui a0, 0x110
c.lw a0, 0x8(a0)
# Test block 4 tests instruction interleaving. Essentially the code's
# ability to keep track of a valid sequence even if multiple other unrelated
# instructions separate the two.
- lui a0, 0x2
+ lui a0, 0x10
lui a1, 0x1 # Unrelated instruction.
slli t1, t1, 0x1 # Unrelated instruction.
addi a0, a0, 0x4
@@ -74,23 +72,21 @@ _start:
# relative to the zero register trigger address resolution. The latter kind
# of instructions are essentially memory accesses relative to the zero
# register.
- lui x0, 0x200
- sw a0, 0x8(x0)
+ fsw f0, 0x8(x0)
# Test 6 ensures that the newly added functionality is compatible with
# code that already worked for branch instructions.
call func
# Test #7 -- zcb extension.
- lui x8, 0x3
+ lui x8, 0x11
c.sb x8, 0(x8)
# Test #8 -- stack based load/stores.
c.lwsp a0, 0x8(sp)
# These are the labels that the instructions above are expected to resolve to.
-.section .data
-.skip 0x4
+.skip 0xffc4
target:
.word 1
.skip 0xff8
>From 86d6bd5eb835467d40d5f8e4321c55710139ad68 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Mon, 23 Jun 2025 20:16:27 -0400
Subject: [PATCH 11/13] Update comments
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index a51f5a05b0fbb..16aaf1d77d78f 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2432,7 +2432,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
break;
}
- // Branch and instruction targets are printed just after the instructions.
+ // Instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
bool BBAddrMapLabelAvailable = BBAddrMapLabels.count(Target);
bool LabelAvailable = AllLabels.count(Target);
>From 1e1a37ce4df131c552962f4c3ad23ff0822e7382 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Tue, 24 Jun 2025 12:36:29 -0400
Subject: [PATCH 12/13] Differentiate comments in tests from llvm-lit
directives
---
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 10 ++--
.../llvm-objdump/RISCV/riscv64-ar-coverage.s | 56 +++++++++----------
2 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
index 2aa617bf3e8b4..a730ff0788c12 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -10,17 +10,17 @@
# CHECK-NEXT 10: 00c53523 sd a2, 0xa(a0) <target>
# CHECK-NEXT 14: 0000 unimp
-# The structure of this test file is similar to that of riscv64-ar-coverage
-# with the major difference being that these tests are focused on instructions
-# for 32 bit architecture.
+## The structure of this test file is similar to that of riscv64-ar-coverage
+## with the major difference being that these tests are focused on instructions
+## for 32 bit architecture.
.global _start
.text
_start:
auipc a0, 0x0
- addi a0, a0, 0x16 # addi -- behavior changes with different architectures.
+ addi a0, a0, 0x16 ## addi -- behavior changes with different architectures.
- # Test Zclsd and Zilsd instructions respectively
+ ## Test Zclsd and Zilsd instructions respectively
auipc a0, 0x0
c.ld a2, 0x10(a0)
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index 7c129bd7b8a0b..3d2dda4bd673a 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -26,66 +26,66 @@
# CHECK-NEXT: 3c: 8800 sb s0, 0x0(s0) <zcb>
# CHECK-NEXT: 3e: 4522 lw a0, 0x8(sp)
-# The core of the feature being added was address resolution for instruction
-# sequences where a register is populated by immediate values via two
-# separate instructions. First by an instruction that provides the upper bits
-# (auipc, lui, etc) followed by another instruction for the lower bits (addi,
-# jalr, ld, etc.).
+## The core of the feature being added was address resolution for instruction
+## sequences where a register is populated by immediate values via two
+## separate instructions. First by an instruction that provides the upper bits
+## (auipc, lui, etc) followed by another instruction for the lower bits (addi,
+## jalr, ld, etc.).
.global _start
.text
_start:
- # Test block 1-3 each focus on a certain starting instruction in a sequence.
- # Starting instructions are the ones that provide the upper bits. The other
- # instruction in the sequence is the one that provides the lower bits. The
- # second instruction is arbitrarily chosen to increase code coverage.
+ ## Test block 1-3 each focus on a certain starting instruction in a sequence.
+ ## Starting instructions are the ones that provide the upper bits. The other
+ ## instruction in the sequence is the one that provides the lower bits. The
+ ## second instruction is arbitrarily chosen to increase code coverage.
- # Test block #1.
+ ## Test block #1.
lla a0, target
auipc a0, 0x10
c.addi a0, -0x4
- # Test block #2.
+ ## Test block #2.
c.lui a0, 0x10
addiw a1, a0, 0x4
c.lui a0, 0x10
c.addiw a0, 0x4
- # Test block #3.
+ ## Test block #3.
lui a0, 0x110
sw a1, 0x8(a0)
lui a0, 0x110
c.lw a0, 0x8(a0)
- # Test block 4 tests instruction interleaving. Essentially the code's
- # ability to keep track of a valid sequence even if multiple other unrelated
- # instructions separate the two.
+ ## Test block 4 tests instruction interleaving. Essentially the code's
+ ## ability to keep track of a valid sequence even if multiple other unrelated
+ ## instructions separate the two.
lui a0, 0x10
- lui a1, 0x1 # Unrelated instruction.
- slli t1, t1, 0x1 # Unrelated instruction.
+ lui a1, 0x1 ## Unrelated instruction.
+ slli t1, t1, 0x1 ## Unrelated instruction.
addi a0, a0, 0x4
- addi a0, a0, 0x1 # Verify register tracking terminates.
+ addi a0, a0, 0x1 ## Verify register tracking terminates.
- # Test 5 checks instructions providing upper bits do not change the tracked
- # value of zero register. Also ensures load/store instructions accessing data
- # relative to the zero register trigger address resolution. The latter kind
- # of instructions are essentially memory accesses relative to the zero
- # register.
+ ## Test 5 checks instructions providing upper bits do not change the tracked
+ ## value of zero register. Also ensures load/store instructions accessing data
+ ## relative to the zero register trigger address resolution. The latter kind
+ ## of instructions are essentially memory accesses relative to the zero
+ ## register.
fsw f0, 0x8(x0)
- # Test 6 ensures that the newly added functionality is compatible with
- # code that already worked for branch instructions.
+ ## Test 6 ensures that the newly added functionality is compatible with
+ ## code that already worked for branch instructions.
call func
- # Test #7 -- zcb extension.
+ ## Test #7 -- zcb extension.
lui x8, 0x11
c.sb x8, 0(x8)
- # Test #8 -- stack based load/stores.
+ ## Test #8 -- stack based load/stores.
c.lwsp a0, 0x8(sp)
-# These are the labels that the instructions above are expected to resolve to.
+## These are the labels that the instructions above are expected to resolve to.
.skip 0xffc4
target:
.word 1
>From b2a89280b222f853a56143d151dbff1fa3ad94ed Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Thu, 26 Jun 2025 00:45:41 -0400
Subject: [PATCH 13/13] Merge evaluateInstruction into evaluateBranch
The functionality of both the functions was very similar with the only difference being that addi needed to know the width of the registers. This information is supplied by MCSubtargetInfo which is passed in as a parameter when instructions that need the register width can be emitted in the disassembly and set to the default of nullptr otherwise
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 2 +-
llvm/lib/MC/MCInstrAnalysis.cpp | 6 +++---
.../MCTargetDesc/AArch64MCTargetDesc.cpp | 2 +-
.../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 2 +-
.../ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 2 +-
.../BPF/MCTargetDesc/BPFMCTargetDesc.cpp | 2 +-
.../CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp | 2 +-
.../MCTargetDesc/HexagonMCTargetDesc.cpp | 2 +-
.../Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp | 2 +-
.../MCTargetDesc/LoongArchMCTargetDesc.cpp | 2 +-
.../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 2 +-
.../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 2 +-
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 19 ++++++-------------
.../X86/MCTargetDesc/X86MCTargetDesc.cpp | 4 ++--
llvm/tools/llvm-objdump/llvm-objdump.cpp | 5 +----
15 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index a0411a365791a..3a55e342de901 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -181,7 +181,7 @@ class LLVM_ABI MCInstrAnalysis {
/// targets. Return true on success, and the address in Target.
virtual bool
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const;
+ uint64_t &Target, const MCSubtargetInfo *STI = nullptr) const;
/// Given an instruction that accesses a memory address, try to compute
/// the target address. Return true on success, and the address in \p Target.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index d726b1c0eabbe..47a9f4429c403 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -24,9 +24,9 @@ bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
return false;
}
-bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
- uint64_t /*Size*/,
- uint64_t & /*Target*/) const {
+bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size,
+ uint64_t &Target, const MCSubtargetInfo *STI) const {
return false;
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
index b7959e02ec268..c52e807703a9b 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -394,7 +394,7 @@ class AArch64MCInstrAnalysis : public MCInstrAnalysis {
AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
// Search for a PC-relative argument.
// This will handle instructions like bcc (where the first argument is the
// condition code) and cbz (where it is a register).
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index c692895d84c00..406cb647e3a8a 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -137,7 +137,7 @@ class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
Info->get(Inst.getOpcode()).operands()[0].OperandType !=
MCOI::OPERAND_PCREL)
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index c756bff3b501a..7d6e43f575f94 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -413,7 +413,7 @@ class ARMMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
// Find the PC-relative immediate operand in the instruction.
diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
index caf84701b999f..7518294437463 100644
--- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
+++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
@@ -77,7 +77,7 @@ class BPFMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
// The target is the 3rd operand of cond inst and the 1st of uncond inst.
int32_t Imm;
if (isConditionalBranch(Inst)) {
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
index bb122f683644b..550d10f60fbd9 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
@@ -113,7 +113,7 @@ class CSKYMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
if (isConditionalBranch(Inst) || isUnconditionalBranch(Inst)) {
int64_t Imm;
Imm = Inst.getOperand(Inst.getNumOperands() - 1).getImm();
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 91051cd4e2d51..131fd3053d46d 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -717,7 +717,7 @@ class HexagonMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target) const override {
+ uint64_t Size, uint64_t &Target, const MCSubtargetInfo *STI) const override {
if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
isConditionalBranch(Inst)))
return false;
diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
index 4a381c033b384..a53050e1b5f95 100644
--- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
+++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
@@ -94,7 +94,7 @@ class LanaiMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
if (Inst.getNumOperands() == 0)
return false;
if (!isConditionalBranch(Inst) && !isUnconditionalBranch(Inst) &&
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
index 3ec070e5cbdd3..a3f1d50f321bb 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
@@ -100,7 +100,7 @@ class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
unsigned NumOps = Inst.getNumOperands();
if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
Inst.getOpcode() == LoongArch::BL) {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index add36d87b9eff..d889f25bb9ea7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -231,7 +231,7 @@ class MipsMCInstrAnalysis : public MCInstrAnalysis {
MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
unsigned NumOps = Inst.getNumOperands();
if (NumOps == 0)
return false;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
index 03a034182ae15..e6abe37bf12a0 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
@@ -456,7 +456,7 @@ class PPCMCInstrAnalysis : public MCInstrAnalysis {
: MCInstrAnalysis(Info) {}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
unsigned NumOps = Inst.getNumOperands();
if (NumOps == 0 ||
Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType !=
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 2a8572cb7b414..8ce18c539d14f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -210,7 +210,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo *STI) const override {
if (isConditionalBranch(Inst)) {
int64_t Imm;
if (Size == 2)
@@ -222,6 +222,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
+ default:
+ return false;
case RISCV::C_J:
case RISCV::C_JAL:
case RISCV::QC_E_J:
@@ -238,20 +240,11 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
return false;
}
- }
-
- return false;
- }
-
- bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target,
- const MCSubtargetInfo &STI) const override {
- unsigned int ArchRegWidth = STI.getTargetTriple().getArchPointerBitWidth();
- switch(Inst.getOpcode()) {
- default:
- return false;
case RISCV::C_ADDI:
case RISCV::ADDI: {
+ if (!STI)
+ return false;
+ unsigned int ArchRegWidth = STI->getTargetTriple().getArchPointerBitWidth();
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
if (TargetRegState && Reg != RISCV::X0) {
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 2eb22b239aa48..adc5bdb63cfbb 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -515,7 +515,7 @@ class X86MCInstrAnalysis : public MCInstrAnalysis {
const MCSubtargetInfo &STI) const override;
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override;
+ uint64_t &Target, const MCSubtargetInfo *STI) const override;
std::optional<uint64_t>
evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
uint64_t Addr, uint64_t Size) const override;
@@ -641,7 +641,7 @@ X86MCInstrAnalysis::findPltEntries(uint64_t PltSectionVA,
}
bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target) const {
+ uint64_t Size, uint64_t &Target, const MCSubtargetInfo *STI = nullptr) const {
if (Inst.getNumOperands() == 0 ||
Info->get(Inst.getOpcode()).operands()[0].OperandType !=
MCOI::OPERAND_PCREL)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 16aaf1d77d78f..fc8dfd78c481d 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2356,10 +2356,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
- Inst, SectionAddr + Index, Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target,
- *DT->SubtargetInfo);
+ Inst, SectionAddr + Index, Size, Target, DT->SubtargetInfo.get());
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
More information about the llvm-commits
mailing list