[llvm] [WebAssembly] [Backend] Wasm optimize illegal bitmask (PR #145627)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 25 11:40:51 PDT 2025
badumbatish wrote:
i'm finding out that in web assembly, in llvm ir, v64i8 can be converted to 4 v128 as input to the selection dag, but v64i4 will degenerate to 64 integers of i32. I'm not sure how to handle this case so that v64i4 can be converted to 2 v128?
I set it via WebAssembly::getPreferredVectorAction so that if (EltVT == MVT::v64i4) return TypeSplitVector;
the only place that calls this function in TargetLoweringBase is computeRegisterProperties.
The enum fall throughs to TypeScalarizeVector (below is the block for it in computeRegisterProperties), but after this i'm not sure where to go next
case TypeScalarizeVector: {
MVT IntermediateVT;
MVT RegisterVT;
unsigned NumIntermediates;
unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
NumIntermediates, RegisterVT, this);
NumRegistersForVT[i] = NumRegisters;
assert(NumRegistersForVT[i] == NumRegisters &&
"NumRegistersForVT size cannot represent NumRegisters!");
RegisterTypeForVT[i] = RegisterVT;
MVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
TransformToType[i] = MVT::Other;
if (PreferredAction == TypeScalarizeVector)
ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
else if (PreferredAction == TypeSplitVector)
ValueTypeActions.setTypeAction(VT, TypeSplitVector);
else if (EC.getKnownMinValue() > 1)
ValueTypeActions.setTypeAction(VT, TypeSplitVector);
else
ValueTypeActions.setTypeAction(VT, EC.isScalable()
? TypeScalarizeScalableVector
: TypeScalarizeVector);
} else {
TransformToType[i] = NVT;
ValueTypeActions.setTypeAction(VT, TypeWidenVector);
}
break;
}
https://github.com/llvm/llvm-project/pull/145627
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