[llvm] [DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (PR #145298)

[via llvm-commits]

woruyu wrote:

So based on my understanding of all the testcase changes, I think:
1. we need to add extra pattern (VSELECT setgt, iN lhs, -1, 1, -1) to DAGCombine and remove from arm64.
2. for andnot, just keep in x86 backend.
3. for exchange of register position, just ignore
4. for other testcase, I think bool instruction is better than vector select instruction, it's an optimization.

@arsenm @RKSimon Any suggestion for this pr or my options

https://github.com/llvm/llvm-project/pull/145298