[llvm] [RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing compare with x0. NFC (PR #145440)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 24 12:49:08 PDT 2025
================
@@ -1464,11 +1467,14 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
modifyBranch();
return true;
}
- } else if (isFromLoadImm(MRI, RHS, C0) && MRI.hasOneUse(RHS.getReg())) {
+ }
+ } else if (isFromLoadImm(MRI, RHS, C0) && RHS.getReg().isVirtual() &&
+ MRI.hasOneUse(RHS.getReg())) {
+ assert(isInt<12>(C0) && "Unexpected immediate");
// Might be case 2.
- // For unsigned cases, we don't want C1 to wrap back to UINT64_MAX
- // when C0 is zero.
- if ((CC == RISCVCC::COND_GE || CC == RISCVCC::COND_LT) || C0)
+ // For signed cases we don't want to change 0 since we can use x0.
+ // For unsigned cases changing 0 to -1U would be incorrect.
+ if (C0) {
if (Register RegZ = searchConst(C0 - 1)) {
----------------
preames wrote:
Ah! That was the bit I was missing. We can't have INT_MIN here until we handle LUI/ADDI sequences.
https://github.com/llvm/llvm-project/pull/145440
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