[llvm] [NVPTX] Allow directly storing immediates to improve readability (PR #145552)

[Artem Belevich via llvm-commits]

================
@@ -2158,6 +2157,19 @@ bool NVPTXDAGToDAGISel::SelectADDR(SDValue Addr, SDValue &Base,
   return true;
 }
 
+SDValue NVPTXDAGToDAGISel::selectPossiblyImm(SDValue V) {
+  if (V.getOpcode() == ISD::BITCAST)
+    V = V.getOperand(0);
----------------
Artem-B wrote:

Can we ever see a chain of multiple bitcasts here?
E.g v4i8->v2i16->v2f16->i32, with each stage value used for something/escaping, so they are not optimized right away? 

Expecting a singleton bitcast looks like an oddly specific case to me. We should either expect none, or expect a potentially arbitrarily long chain of them. What am I missing? Is there a reason we're expecting at most one bitcast?



https://github.com/llvm/llvm-project/pull/145552