[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

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@@ -4056,6 +4056,53 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
+  // When the shl64_reduce optimisation code is passed through vector
+  // legalization some scalarising occurs. After ISD::AND was legalised, this
+  // resulted in the AND instructions no longer being elided, as mentioned
+  // below. The following code should make sure this takes place.
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chrisjbris wrote:

thanks, i'll remove the comments. The combiner issue is common to to all the new shift64_reduce optimisations e.g. https://github.com/chrisjbris/llvm-project/commit/c4caf00bfbf10caa88f1c46a561564b4f0f723af

https://github.com/llvm/llvm-project/pull/140694