[llvm] [RISCV] Optimize vp.splice with 0 offset. (PR #145533)

[Philip Reames via llvm-commits]

https://github.com/preames approved this pull request.

LGTM

Another case here possibly worth optimizing - if index is zero, and evla is a multiple of a register size, the slideup can become a whole register move.  

Though, maybe some of this should be done at IR instead of DAG?  I can't quite see how to frame this transform, but the one I just proposed could be a vector extract/insert.  

https://github.com/llvm/llvm-project/pull/145533