[llvm] [RISCV] Try to optimize `vp.splice` to `vslide1up`. (PR #144871)

[Craig Topper via llvm-commits]

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@@ -13282,6 +13284,30 @@ RISCVTargetLowering::lowerVPSpliceExperimental(SDValue Op,
                       SplatZeroOp2, DAG.getUNDEF(ContainerVT), EVL2);
   }
 
+  auto getVectorFirstEle = [](SDValue Vec) {
+    SDValue FirstEle;
+    if (sd_match(Vec, m_InsertElt(m_Value(), m_Value(FirstEle), m_Zero())))
+      return FirstEle;
+
+    if (sd_match(Vec,
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topperc wrote:

You can just use `Vec.getOpcode() == ISD::SPLAT_VECTOR || Vec.getOpcode() == ISD::BUILD_VECTOR`. There's no reason to use `sd_match` if you're not matching a pattern.

https://github.com/llvm/llvm-project/pull/144871